Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 9, 2021 Abstract: The Accelera Universal Verification Methodology (UVM) became an IEEE standard published as IEEE 1800.2 – IEEE Standard for UVM Language Reference Manual (LRM). UVM has been the predominant verification methodology for ASIC designs for many years and has recently gained popularity and… Read More »UVM for FPGAs (Part 1)