VerifWorksm UVM

Abstract: Today’s FPGAs have become larger in logic density and can handle complex designs with multi-million system logic cells. The traditional verification techniques of simple simulations combined with a detailed validation in the lab simply do not scale up any longer. Even to map a large logic design to a modern-day FPGA takes many hours.… UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM