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Aldec, August 22, 2024

Using OSVVM’s AXI4 Verification Components: Pt 1 Creating the AXI4 Testbench / Test Harness

European Session Abstract: This “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 1 of this presentation provides a detailed walkthrough of creating a… Using OSVVM’s AXI4 Verification Components: Pt 1 Creating the AXI4 Testbench / Test Harness

Aldec, June 23, 2022

Advances in OSVVM’s Verification Data Structures

OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have… Advances in OSVVM’s Verification Data Structures

Aldec, June 16, 2022

OSVVM’s Test Reports and Simulator Independent Scripting

According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging.  As a result, we need good scripting to simplify running tests and good reports to simplify debug and help… OSVVM’s Test Reports and Simulator Independent Scripting

Aldec, June 9, 2022

Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM

Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or the test harness.  SystemVerilog + UVM is certainly like this.… Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM

Aldec, May 26, 2022

Better FPGA Verification with VHDL: OSVVM – Leading Edge Verification for the VHDL Community

OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA verification projects from start to finish. Using these libraries,… Better FPGA Verification with VHDL: OSVVM – Leading Edge Verification for the VHDL Community