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Sunil Sahoo

Aldec, February 24, 2022

Automating UVM flow using Riviera-PRO’s UVM Generator

  • February 24, 2022February 21, 2022

UVM is a versatile verification methodology that enables users to run advanced verification flows for large scale FPGAs and SoC FPGAs. However, because of its… Read More »Automating UVM flow using Riviera-PRO’s UVM Generator

Aldec, January 20, 2022

Increase your productivity with Continuous Integration flows

  • January 20, 2022January 17, 2022

Abstract: In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has… Read More »Increase your productivity with Continuous Integration flows

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