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Freelance EDA Consultant

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Marketing EDA

Freelance EDA Consultant

Home
About
Events
Clients
Services
Blogs
DAC Trip Reports
- DAC 2022
- DAC 2021
- DAC 2020
- DAC 2019
- DAC 2018
- DAC 2017
- DAC 2016
- DAC 2015
- DAC 2014
- DAC 2013
- DAC 2012
- DAC 2011
- DAC 2010
Contact

Virtuoso Layout Suite EXL

Tweets

My Tweets

Mentions in the Press

AMS, RF and Digital Full Custom IC Designs need Circuit Sizing
MunEDA
September 2021
Automating the Design of Flat Panel Displays
Empyrean
October 2020
Xilinx Moves from Internal Flow to Commercial Flow for IP Integration
Empyrean
August 2020
Viewing the Largest IC Layout Files Quickly
Empyrean
March 2020
Where Circuit Simulation Model Files Come From
Silvaco
August 2019
ST, Intento: EDA for Faster Analog Design in FD-SOI
SOI Industry Consortium
July 2018
Predictions about EDA and IP at #52DAC
Design & Reuse
June 2015
Networking at 52nd DAC
DAC
April 2015
WLAN Design Optimization at Lantiq
MunEDA News
January 2015
Gary Smith EDA
Comments
July 2013
Verilog-AMS & Multi-Level Simulation
Aldec blog
July 2013
Daniel Payne reviews new Mixed-Signal Methodology book. He enjoyed it. Discount ends tomorrow!
Steve Leibson
August 30, 2012
DAC 2012 Preview: Focus on Formal and ABV Events and Papers
Cadence blog
May 14, 2012
ClioSoft Celebrates 2011 Year-end with 53% Increase in Bookings
Press Release
March 8, 2012
Mentor spins off product line, takes stake in buyer
Portland Business Journal
August 26, 2011
Establishing a new standard-the #SemiEDA hashtag
Synopsys blog
April 28, 2011
Mentor Graphics right to reject Icahn’s bid
Portland Business Journal
March 28, 2011
Rival Mentor bids could be market grab
Portland Business Journal
February 23, 2011
A New Collaboration for the Semiconductor Industry
Synopsys blog
November 18, 2010
Mentor Graphics rebounds, but Carl Icahn casts a shadow
Oregonian
July 10, 2010
Mentor Graphics waits to hear from Carl Icahn
Portland Business Journal
June 17, 2010
Analyst Newsletter
Cadence
Q2 2009
Tela Innovations – 1D Layout is Good for DFM
July 2009

Address:

10440 SW Kellogg Drive
Tualatin, OR 97062

SemiWiki Blog

Webinar: Post-layout Circuit Sizing Optimization September 26, 2022
Die-to-Die Interconnects using Bunch of Wires (BoW) September 21, 2022
Machine Learning in the Fab at #59DAC September 14, 2022
IC Layout Symmetry Challenges August 29, 2022
Automating and Optimizing an ADC with Layout Generators August 24, 2022

News

Intel Foundry Services, It’s Awakening February 7, 2022
Merry Christmas 2021 December 16, 2021
New Look, Added Events November 10, 2021
What Ever Happened to ChipDesignMag.com April 24, 2021
Another Company Speeds Up SPICE with a GPU April 21, 2021

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