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Austin Verification Seminar
August 25 @ 9:30 am - 2:30 pm CDT
Join Siemens EDA for an in-person seminar focused on hot issues in design verification, and solutions you can implement today.
About this event
Delivering high product quality without sacrificing today’s demanding product schedules means boosting verification productivity and cutting bug escapes. Product development teams must speed time to coverage closure, requiring new and improved technologies that make a meaningful difference in a verification cycle.
9:00 – 9:30
Arrival and check-in
Introductions and networking with your peers.
9:30 – 10:15
Keynote: The state of functional verification: crisis or opportunity?
Presenter: Harry Foster | Chief Scientist Verification
Has the industry finally reached a breaking point in terms of a verification crisis? This talk quantitatively answers this question by presenting the latest industry trends in functional verification based on the 2022 Wilson Research Group Functional Verification Study. Although some of this year’s findings are disturbing, a key point of this talk is to prescribe a holistic and philosophical change in the way we approach design with a foundation based on bug prevention to avert an impending crisis.
10:15 – 10:45
Technology update: Static and formal and the next normal.
Presenter: Chris Giles | Head of Product Management – Static & Formal Technologies
New normals come and go, but the past three years have been a period of monumental and unexpected change. Succeeding in the market today requires more than working harder but doing the same thing. This session will describe how Siemens EDA’s investments in Static and Formal technologies will help you reduce risk exposure now and for the next new normal.
10:45 – 11:30
Productive development via static and formal linting.
Presenter: Walter Gude | Application Engineering Consultant
Static and Formal technologies are each capable of linting RTL to find coding errors and non-compliance before a testbench is ever written. However, each of these solutions has a sweet spot in the development flow. Learn in this session what each contributes to the overall linting solution, and when to use what for maximum efficiency, even in design creation.
11:30 – 12:15
Master-level CDC: Why your CDC methodology is probably working against you.
Presenter: Vinayak Desai | Principal Product Engineer
While some teams still haven’t adopted CDC verification to ensure success, those who have consider the problem solved. This perspective leads to complacency and ignores an entire series of issues that condemn projects into rework that no project can afford today in the era of the next normal. This session will identify the issues that often get overlooked in domain crossing analyses and will provide you with strategies to avoid future failures.
12:15 – 1:00
Lunch will be provided.
1:00 – 1:45
Using Formal technology to secure complex ICs in a connected world.
Presenter: John Hallman| Product Owner – Trust & Security
Aircraft, automobiles, and many other products rely on complex microelectronic components now more than ever to monitor, control and process critical information. This connected world, enabled by these devices, poses increasing challenges to personal safety, financial loss, exposure of personal information, and operation failure. Functional verification of microelectronic devices requires thorough methods and securing the IC in the system requires even more. Siemens’ OneSpin tools and apps have technologies built upon world class formal engines and provide results desired in emerging cybersecurity standards. In this presentation we will introduce apps that provide an automated assessment platform, perform processor verification, and offer completeness checking to perform security verification in your IC.
1:45 – 2:30
Quantify mutation coverage.
Presenter: David Landoll | Solution Architect
For engineers new to property-based verification, their critical questions are typically “How good are the properties I’ve already added?” and “What properties should I add next?” For engineers now proficient at adding properties to their design, their critical questions that remain are “Do my properties cover the entire design?”, “What properties am I missing?”, and “Did I do anything wrong setting up the formal testbench?”. Learn in this session how mutation coverage can answer all these questions and more. Mutation coverage can measure the quality of a formal testbench, provide precise, actionable information on what parts of the design are verified, and highlights RTL code that could still be hiding bugs. Additionally, this technology reveals potential issues in the testbench that might corrupt metrics and give a false sense of confidence.
Seating for this seminar will be limited, please register to save your seat.
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