Versal ACAP Workshop Online
May 24 @ 8:00 am - May 25 @ 5:00 pm PDT
The Xilinx Versal ACAP platform is multi-featured, offering unprecedented system level performance and integration.
This informative workshop (delivered in 2 half day sessions) is a comprehensive and practical introduction to the features and capabilities.
We’ll first cover the broader Versal ACAP device. We’ll then focus on a practical example, optimizing a given application for the AI Engine resources.
The workshop is designed to maximize individual engagement and learning. Each attendee is encouraged to informally ask pertinent questions throughout, to actively participate in the learning process.
Workshop Agenda: Delivered across 2 half-day sessions
– Versal ACAP: Structural Overview Big picture overview, processing engines, connections and capabilities.
– Intro to AI Engines Scalar and vector processing unit, SIMD data-path, multi-kernel control and communication
– PS Overview Introduce the A72 and R5F processors, MPSoC migration, the role of the PMU, device boot, etc.
– PL Fabric The traditional FPGA fabric, encompassing enhanced layout, clocking, and slice capabilities
– NoC Resources Overview for Versal ACAP communication backplane, data-transfer, DDR controller – Enhanced DSP58 New features, layout and operational modes for PL fabric-based DSP building blocks
– AIE Vector Datatypes Declaring vector datatypes required for the high-performance SIMD data-paths – Intrinsic(s) Coding Introduction to proprietary syntax for maximizing AI engine vector processing
– FIR Filter Coding for AIE A step-by-step working example for 1GHz+ FIR filter targeting AI engine
Please come prepared to actively participate and engage directly with the workshop facilitator.
Thanks to Xilinx for sponsoring this training – it is now available to attend Free of Charge.