TechNES FPGA Front Runner Event
New Mills Wotton-under-Edge, United KingdomThe FPGA Front Runners event will be hosted by Renishaw at their venue in Wotton-under-Edge. The event will focus on “Using AI in development and product for FPGA”. If you are interested in speaking at this event please email mike.bartley@techworks.org.uk Topics for talks: What AI support is being built into the FPGA fabrics? How are… Read More »TechNES FPGA Front Runner Event
DFT for chiplets & 3D ICs using Tessent Multi-die
3D IC (2.5D/3D) designs are on the rise. Design for Test (DFT) for chiplets must be general purpose so they can be tested stand alone and easy to test after assembly into 2.5D or 3D devices. In this webinar you will learn how to use Tessent Multi-die and still adhere to standards like IEEE 1149.1,… Read More »DFT for chiplets & 3D ICs using Tessent Multi-die
CXL DevCon 2024
Santa Clara Marriott 2700 Mission College Blvd, Santa Clara, CA, United StatesThe CXL Consortium is looking forward to hosting the first Compute Express Link® (CXL®) DevCon from April 30 – May 1, 2024, in Santa Clara, California! CXL DevCon is a unique opportunity for our Members to learn directly from CXL technology experts. Attendees will participate in CXL technical training, view available products and technology demonstrations,… Read More »CXL DevCon 2024
TSMC 2024 Technology Workshop – Austin
JW Marriott Austin 110 E 2nd St, Austin, TX, United States08:30 – 09:30 Registration & Partner Pavilion 09:30 – 09:40 Welcome & Opening Remarks 09:40 – 10:00 Market Outlook – Powering AI Together 10:00 – 10:30 Advanced Technology Leadership 10:30 – 11:00 Coffee Break & Ecosystem Pavilion 11:00 – 11:25 Specialty Technology Leadership 11:25 – 11:50 Manufacturing Excellence 11:50 – 13:00 Lunch & Ecosystem Pavilion… Read More »TSMC 2024 Technology Workshop – Austin
Smart methods for DFT chip architecture & validation
Combining market-leading design-for-test (DFT) technologies with best-in-class netlist synthesis allows you to achieve DFT success more quickly. Many customers, including those for emulation and IC test, have challenges with scaling architectures. This webinar describes how Siemens emulation and silicon test solutions can work together to provide a smart DFT plug-and-play architecture for Veloce ICs. The… Read More »Smart methods for DFT chip architecture & validation
Keysight EDA Connect Tour – Austin
Topgolf Austin 2700 Esperanza Crossing, Austin, TX, United StatesKeysight is excited to announce the next destination stops of our EDA Connect World Tour: Austin, TX and Burlington, MA. Save the dates for our upcoming events in Austin, TX on May 2 or Burlington, MA on May 16, where we'll explore the future of AI in 6G to 3D Module integration. These technical sessions promise to recharge your… Read More »Keysight EDA Connect Tour – Austin
ChipEx 2024
Tel Aviv Convention Center Rokach Boulevard 101, Tel Aviv, IsraelChipEx2024, the largest annual event of the Israeli semiconductor industry, will be held on May 7-8, 2024 in Tel Aviv, Israel. ChipEx2024 showcases companies including manufacturers, developers and suppliers of advanced hardware technologies & services. It also includes a technical seminar where the world's leading experts address the industry's most relevant issues. The event is… Read More »ChipEx 2024
TSMC Technology Workshop 2024 – Boston
Boston Marriott Burlington One Burlington Mall Road, Burlington, MA, United States08:30 – 09:30 Registration & Partner Pavilion 09:30 – 09:40 Welcome & Opening Remarks 09:40 – 10:00 Market Outlook – Powering AI Together 10:00 – 10:30 Advanced Technology Leadership 10:30 – 11:00 Coffee Break & Ecosystem Pavilion 11:00 – 11:25 Specialty Technology Leadership 11:25 – 11:50 Manufacturing Excellence 11:50 – 13:00 Lunch & Ecosystem Pavilion… Read More »TSMC Technology Workshop 2024 – Boston
AI-Driven 3D System Analysis & Optimization for EM Antenna/RF Problems
Antenna/RF design problems often involve the optimization of many variables, requiring numerous evaluations (EM simulations) using traditional optimization methods. Design engineers need an intelligent, accurate, and easy-to-use simulation platform and analysis solution that reduces repetitive design cycles while increasing user productivity and efficiency. Leveraging an advanced AI-enabled methodology, the Cadence Optimality Intelligent System Explorer delivers… Read More »AI-Driven 3D System Analysis & Optimization for EM Antenna/RF Problems
ESD Alliance CEO/Executive Outlook
Keysight 5301 Stevens Creek Blvd, Building 5, Santa Clara, United StatesKey executives from leading semiconductor EDA and IP companies will gather to discuss the latest industry trends, challenges and opportunities Thursday, May 9, in Santa Clara, California at the annual CEO Executive Outlook, hosted by the Electronic System Design Alliance (ESD Alliance), a SEMI Technology Community, and Keysight Technologies. Registration is open. Kicking off the program, Calista Redmond, CEO of… Read More »ESD Alliance CEO/Executive Outlook
Introduction to the Open-source EDA Ecosystem
Open-source hardware in the European Chips Act Matthew Xuereb, European Commission Free and open-source semiconductor ecosystem Luca Alloatti, Free Silicon Foundation ETS Open-source EDA software and semiconductor design Jean-Paul Chaput, Sorbonne University, Coriolis Foundation European roadmap on the advancement of open-source EDA tools Rihards Novickis, Latvian Institute of Electronics and Computer Science
Ansys – Simulation World 2024
Did you know that simulation helped Pratt & Whitney design a game-changing engine architecture that has saved aircraft operators over a million gallons in fuel? Or that sustainable energy start-up Amogy is using simulation to build a novel, portable, carbon-free energy system to convert ammonia into renewable fuel that will power green transportation solutions of the future? Or that… Read More »Ansys – Simulation World 2024