EDA
Calendar of Events
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1 event,
RISC-V Instruction Set Architecture: Enhancing Computing Power
RISC-V Instruction Set Architecture: Enhancing Computing Power
*Work email required for registration* Don't miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that promises to inspire and inform: - Gain insights into the latest trends shaping chip design. - Learn from industry leaders about the strategies behind successful… Read More »RISC-V Instruction Set Architecture: Enhancing Computing Power
2 events,
ISQED Symposium 2024
A pioneer and leading interdisciplinary conference, the 25thInternational Symposium on Quality Electronic Design (ISQED'24) accepts and promotes original and unpublished papers related to the topics shown below. ISQED'24 theme is AI/ML& Electronic Design, Hardware Security, Quantum Computing, 3D Integration, and IoT. Authors are invited to submit papers in following topics (please visit the website for… Read More »ISQED Symposium 2024
Siemens EDA User2User Conference
Engineer a smarter future, faster at Siemens EDA User2User Conference April 3-4, 2024 Santa Clara, CA. Join your colleagues from around the industry for a day of technical sessions, networking, keynote sessions, labs and more. User2User is free of charge for Siemens EDA customers and includes sessions, lunch, and parking. Technology tracks covering the latest… Read More »Siemens EDA User2User Conference
5 events,
Maximizing the Benefits of Virtuoso Layout Suite XL
Maximizing the Benefits of Virtuoso Layout Suite XL
Find out how the Virtuoso Layout Suite XL you’ve known for many years is setting new standards in custom layout authoring. The connectivity-driven paradigm keeps the layout in synch with the circuit design and ensures that the design intents are always honored. Learn how we strengthened the layout editor in Virtuoso Studio, launched in 2023,… Read More »Maximizing the Benefits of Virtuoso Layout Suite XL
Hierarchical Analysis of EM Crosstalk with EMX Planar 3D Solver
Hierarchical Analysis of EM Crosstalk with EMX Planar 3D Solver
Identifying sources of electromagnetic (EM) coupling and safeguarding today’s complex electronic designs from EM crosstalk are daunting tasks. For designs with multiple levels of hierarchy, identification, and detailed analysis of the “EM-sensitive” content is a challenge. The manual creation of wrapper cells or new layout views to enable this quickly becomes a time-consuming and error-prone… Read More »Hierarchical Analysis of EM Crosstalk with EMX Planar 3D Solver
High-Performance RTL Simulation Workflow with Libero and Active-HDL
High-Performance RTL Simulation Workflow with Libero and Active-HDL
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs).… Read More »High-Performance RTL Simulation Workflow with Libero and Active-HDL
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3 events,
Embedded World 2024
The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community, including leading experts, key players and industry associations. It offers unprecedented insight into the world of embedded systems, from components and modules to operating systems, hardware and software design, M2M communication, services, and various issues related to… Read More »Embedded World 2024
Ansys 2024 R1: High Frequency Electronics What’s New
Ansys 2024 R1: High Frequency Electronics What’s New
Learn about the latest improvements and new features to the high frequency electronics simulation tools. There are many enhancements for engineers involved in RF, automotive, A&D, and consumer electronics designs that our subject matter experts will discuss. Overview This Ansys 2024 R1 webinar will review the high-frequency electronics tool updates, enhancements, and new features –… Read More »Ansys 2024 R1: High Frequency Electronics What’s New
Guiding your aerospace electrical journey
Guiding your aerospace electrical journey
Aerospace electrical/electronic (EE) design requires a delicate balance between innovative technology and uncompromising reliability. Meanwhile, the pressure to get products to market faster is growing exponentially. Finding ways to design electrical systems quickly, cost-effectively and efficiently has become a central focus of manufacturers. Siemens has the solutions and partnerships to guide the development of best-in-class… Read More »Guiding your aerospace electrical journey
2 events,
Virtuoso – Finding Hidden Treasures to Accelerate Routing Your Layout
Virtuoso – Finding Hidden Treasures to Accelerate Routing Your Layout
Every layout designer frets over routing all the interconnects DRC clean and correct as per the circuit designer’s expectations. On the one hand, you want a magic wand that just hooks up all the connections with perfect smartness. On the other hand, you need to guide the connections carefully while weaving your own creative magic… Read More »Virtuoso – Finding Hidden Treasures to Accelerate Routing Your Layout
4 events,
Siemens EDA – TechDay Grenoble 2024
Siemens EDA – TechDay Grenoble 2024
Siemens EDA Technology Day in Grenoble is your opportunity to learn, grow and connect with fellow technical experts who design leading-edge products using Siemens EDA tools. This event is dedicated to end users of Siemens EDA solutions. This conference is free to attend and includes keynotes from industry leaders and enriching technical sessions. Analog/Mixed-Signal… Read More »Siemens EDA – TechDay Grenoble 2024
Cadence Managed Cloud for Cost Efficient and Productive Chip Design
Cadence Managed Cloud for Cost Efficient and Productive Chip Design
Join us for an informative webinar, as we unveil the capabilities of our cloud solutions designed to revolutionize EDA workloads. Whether you require completely hosted environments or need peak/burst capacity, our cloud solutions offer unparalleled flexibility and efficiency. We will discuss how Cadence Managed Cloud can optimize cost-efficiency and productivity for your chip design projects.… Read More »Cadence Managed Cloud for Cost Efficient and Productive Chip Design
Making a Structured VHDL Testbench – A Demo for Beginners
Making a Structured VHDL Testbench – A Demo for Beginners
Abstract: This demonstrated tutorial is intended for designers and verification engineers who want to learn to make better and more structured testbenches. This session will show you what is needed for any good testbench, irrespective of its complexity. We will make a testbench from scratch for a simple VHDL module and do the following: Add… Read More »Making a Structured VHDL Testbench – A Demo for Beginners
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1 event,
Open Source Summit – North America
Open Source Summit – North America
Registration Cost: $15 This half day program will Introduce the audience to the many aspects of open source hardware and software development, and how it is helping the industry to accelerate beyond what Moore’s law has predicted. Talks will cover numerous aspects of hardware / software development and provide motivation to learn more about the challenges… Read More »Open Source Summit – North America
4 events,
CS Inernational Conference
he 14th CS International builds on the strengths of its predecessors, with around 40 leaders from industry and academia delivering presentations that fall within five key themes: Ensuring SiC’s Phenomenal Success; Expanding Horizons for Surface Emitters; Accelerating the Growth of GaN; Taking Power from the Photon; and New Frontiers for the LED. Those attending these… Read More »CS Inernational Conference
Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim
Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim
Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process. Learn how the latest innovations in QuestaSim address these challenges by enabling full off-line… Read More »Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim
Streamline MMIC Design Efficiency with Intelligent Design Data Management
Streamline MMIC Design Efficiency with Intelligent Design Data Management
In the fast-evolving world of monolithic microwave integrated circuit (MMIC) design, meeting higher-frequency requirements is just the beginning. Are you seeking insights on achieving dimensional accuracy for both analog and RF components? Wondering about the automatic synchronization of schematics and layouts across various electronic design automation (EDA) tools? Trusted by hundreds of IC design organizations… Read More »Streamline MMIC Design Efficiency with Intelligent Design Data Management
3 events,
CadenceLIVE Silicon Valley 2024
CadenceLIVE Silicon Valley 2024
Join us for CadenceLIVE Silicon Valley 2024 on April 17 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings users, developers, and industry experts together to connect, share ideas, and inspire design creativity. Attendees have the opportunity… Read More »CadenceLIVE Silicon Valley 2024
Introduction to ParagonX
Introduction to ParagonX
Are you ready to supercharge your design process? Introducing our Diakopto Training Program - your gateway to a faster, easier, and more intuitive approach to design analysis and optimization! In this course, you'll learn how to: Analyze and visualize layout parasitics with precision using R/C/delay/I maps. Perform net matching for accurate and refined designs. Identify… Read More »Introduction to ParagonX
2 events,
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
1 event,
Latch-Up 2024: Boston
Friday to Sunday April 19–21, 2024 in Boston, MA, USA The Latch-Up conference is a weekend of presentations and networking dedicated to free and open source silicon. It's an event for the open source digital design community, much like its European sister conference ORConf, run by the FOSSi Foundation. You are all invited! The FOSSi… Read More »Latch-Up 2024: Boston
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CICC 2024
The IEEE Custom Integrated Circuits Conference is a premier conference devoted to IC development. The conference program is a blend of oral presentations, exhibits, panels and forums. The conference sessions present original first published technical work and innovative circuit techniques that tackle practical problems. CICC is the conference to find out how to solve design… Read More »CICC 2024
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4 events,
osmosis Aerospace and Defense 2024 A Formal Verification Virtual Event
osmosis Aerospace and Defense (A&D) is about sharing the success in using formal techniques to address the demanding verification requirements and challenges of DO-254 compliant and other high-consequence systems. We have put together the following program covering a wide range of formal verification topics. Day 1 - Tuesday, April 23 10:00am Pacific | 1:00pm… Read More »osmosis Aerospace and Defense 2024 A Formal Verification Virtual Event
Siemens User2User Verification Forum 2024 India
Siemens User2User Verification Forum 2024 India
Join us at the Siemens User2User Verification Forum 2024 in India next week! Gain insights on Smart Verification - Using AI in Functional Verification and learn best practices in design and verification flows that can speed up your ASIC and FPGA design & verification cycle. Don't miss the chance to leverage AI and ML based… Read More »Siemens User2User Verification Forum 2024 India
DVClub Europe – Formal Verification
DVClub Europe – Formal Verification
13 days to go the next DVClub Europe meeting takes place on Tuesday 23rd April with a theme of "Formal Verification". Formal Verification can help you find bugs earlier in the design cycle and accelerate root cause analysis. But success with Formal requires the effective selection and implementation of the right formal technologies and methods. In this DVClub meeting… Read More »DVClub Europe – Formal Verification
3 events,
Deploying Solido Design Environment AI Workflows on AWS
Deploying Solido Design Environment AI Workflows on AWS
Utilizing AWS cloud resources to accelerate variation-aware verification AI-powered Solido Design Environment provides SPICE-accurate variation-aware verification for 3, 4, 5, 6 and higher sigma targets, orders of magnitude faster than traditional brute-force methods. With cloud computing made more accessible than before, many teams are considering running design and verification workloads, including Solido Design Environment, on… Read More »Deploying Solido Design Environment AI Workflows on AWS
4 events,
The Era of Software-Defined Everything: Chiplets and Bespoke Silicon
The Era of Software-Defined Everything: Chiplets and Bespoke Silicon
From fintech to automotive, defense to healthcare, everyone wants bespoke computing platforms to build "software-defined solutions" that are differentiated in their respective markets. Sign up and save your spot for this special presentation. Overview With the advent of 3D ICs and heterogeneous semiconductor integration, mapping a system on a customized chip/hardware is accessible to "everyone.”… Read More »The Era of Software-Defined Everything: Chiplets and Bespoke Silicon
Siemens User2User Verification Forum 2024 India
Siemens User2User Verification Forum 2024 India
Join us at the Siemens User2User Verification Forum 2024 in India next week! Gain insights on Smart Verification - Using AI in Functional Verification and learn best practices in design and verification flows that can speed up your ASIC and FPGA design & verification cycle. Don't miss the chance to leverage AI and ML based… Read More »Siemens User2User Verification Forum 2024 India
Improving Semiconductor Wafer Fabrication Process Efficiencies Using Ansys Solutions
Improving Semiconductor Wafer Fabrication Process Efficiencies Using Ansys Solutions
Ansys Semiconductor Manufacturing Webinar Series: Part 1 of 3. Join us on Thursday, April 25th for an in-depth view of multi-physics simulation in the semiconductor fabrication process. Overview Accurate design and optimization of the semiconductor fabrication process/equipment for yield improvements and faster time-to-market require multiphysics simulation, which can address various physical interactions and phenomena. By… Read More »Improving Semiconductor Wafer Fabrication Process Efficiencies Using Ansys Solutions
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DFT for chiplets & 3D ICs using Tessent Multi-die
DFT for chiplets & 3D ICs using Tessent Multi-die
3D IC (2.5D/3D) designs are on the rise. Design for Test (DFT) for chiplets must be general purpose so they can be tested stand alone and easy to test after assembly into 2.5D or 3D devices. In this webinar you will learn how to use Tessent Multi-die and still adhere to standards like IEEE 1149.1,… Read More »DFT for chiplets & 3D ICs using Tessent Multi-die
3 events,
TSMC 2024 Technology Workshop – Austin
TSMC 2024 Technology Workshop – Austin
08:30 – 09:30 Registration & Partner Pavilion 09:30 – 09:40 Welcome & Opening Remarks 09:40 – 10:00 Market Outlook – Powering AI Together 10:00 – 10:30 Advanced Technology Leadership 10:30 – 11:00 Coffee Break & Ecosystem Pavilion 11:00 – 11:25 Specialty Technology Leadership 11:25 – 11:50 Manufacturing Excellence 11:50 – 13:00 Lunch & Ecosystem Pavilion… Read More »TSMC 2024 Technology Workshop – Austin
Smart methods for DFT chip architecture & validation
Smart methods for DFT chip architecture & validation
Combining market-leading design-for-test (DFT) technologies with best-in-class netlist synthesis allows you to achieve DFT success more quickly. Many customers, including those for emulation and IC test, have challenges with scaling architectures. This webinar describes how Siemens emulation and silicon test solutions can work together to provide a smart DFT plug-and-play architecture for Veloce ICs. The… Read More »Smart methods for DFT chip architecture & validation
Keysight EDA Connect Tour – Austin
Keysight EDA Connect Tour – Austin
Keysight is excited to announce the next destination stops of our EDA Connect World Tour: Austin, TX and Burlington, MA. Save the dates for our upcoming events in Austin, TX on May 2 or Burlington, MA on May 16, where we'll explore the future of AI in 6G to 3D Module integration. These technical sessions promise to recharge your… Read More »Keysight EDA Connect Tour – Austin