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Maximize Productivity with Deep Insights into PPA Trajectories
The digital chip design flow carries with it an enormous wealth of untapped information regarding the health and status of your SoC design. The ability to efficiently mine this data provides chip designers with comprehensive visibility and actionable insights to uncover PPA opportunities. This webinar will introduce you to Synopsys Design.da, the industry’s first comprehensive data-visibility… Maximize Productivity with Deep Insights into PPA Trajectories
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Efficient Way to UVM Constraint Randomization Debug
Become skilled at the art of UVM randomization debugging! Date: Wednesday, July 17, 2024 Time: 10:00am PDT | 1:00pm EDT This webinar equips you with effective strategies to tackle randomization-related errors within your UVM verification environment. We'll explore the power of Cadence's Verisium Debug, a tool designed to simplify the debugging process. What You Will Learn Practical… Efficient Way to UVM Constraint Randomization Debug
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Enhancing Manufacturing Test Flows with Synopsys VC Z01X
Leveraging functional patterns is crucial for achieving high defect coverage and reducing defective parts per million (DPPM) levels. Synopsys VC Z01X fault simulator offers enhanced fault coverage in manufacturing test flows, complementing ATPG tools like Synopsys TestMAX ATPG. In this presentation we will delve into unique coverage scenarios, such as resets and clocks blocked during ATPG mode. We'll… Enhancing Manufacturing Test Flows with Synopsys VC Z01X
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SNUG India 2024
Sheraton Grand Bengaluru Whitefield Bengaluru, IndiaSince 1991, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today, as the electronics industry’s largest user conference, SNUG brings together over 12,000 Synopsys tool and technology users across North America, Europe, Asia, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from… SNUG India 2024
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ITC India 2024
Radisson Blu Outer King Road, Bengaluru, IndiaInternational Test Conference is the world’s premier venue dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis, reliability and failure analysis, and back to process and design improvement. At ITC India, design, test, and yield professionals can confront challenges… ITC India 2024
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30th Siemens Xcelerator Technology Innovation Awards
Join us as we name the winners of the most prestigious design contest in PCB — the 30th Siemens Xcelerator Technology Innovation Awards! During this live event, we will announce winners in multiple categories representing a wide variety of design types. Hear from leading industry experts as they discuss features that make these printed circuit… 30th Siemens Xcelerator Technology Innovation Awards
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Simulating AMD’s next-gen Versal Adaptive SoC devices using Questasim
Versal Adaptive SoC, a revolutionary adaptable platform developed by AMD, integrates several key components such as the AI Engine (AIE), Processing System (PS), Programmable Logic (PL), Network on Chip (NoC), and a diverse array of specialized IPs. This innovative platform facilitates the efficient execution of intricate algorithms spanning from machine learning to high-performance computing tasks.… Simulating AMD’s next-gen Versal Adaptive SoC devices using Questasim
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Chiplets: Building the Future of SoCs
Chiplets, also known as heterogeneous multi-die systems, are increasingly seen as the future of System on Chips (SoCs). They offer a solution to meet the growing demands of high-performance computing in various industries, particularly fueled by the widespread adoption of AI technology. However, while the concept of using chiplets to construct larger chips to overcome… Chiplets: Building the Future of SoCs
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Applying Artificial Intelligence in Fab Technology Co-Optimization
The common approach to optimize a fabrication process involves process and fab engineers creating and setting up Design of Experiments (DoEs) using a trial-and-error approach. This approach often leads to costly iterations since wafer fabrication is both expensive and time-consuming. Typically, it can take weeks to months of experimentation, depending on what process parameters are… Applying Artificial Intelligence in Fab Technology Co-Optimization
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Future of Memory and Storage – 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesFMS: the Future of Memory and Storage is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It is the one-stop place to catch up on the latest technologies, see the hottest products, and learn about what's happening and where the latest trends are heading. FMS is now… Future of Memory and Storage – 2024
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Fab.da: Comprehensive AI-Driven Process Analytics for Faster Ramp and Efficient High-Volume Manufacturing
The challenges before semiconductor fabs are expansive and evolving. As the size of chips shrinks from nanometers to eventually angstroms, the complexity of the manufacturing process increases in response. To combat the complexity and sheer intricacy of semiconductor manufacturing, innovative software solutions are required. Synopsys Fab.da is a comprehensive process control solution that utilizes artificial intelligence (AI)… Fab.da: Comprehensive AI-Driven Process Analytics for Faster Ramp and Efficient High-Volume Manufacturing
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Modeling and Simulation of Silicon Photonics Systems in SystemVerilog
Silicon photonics systems integrate photonic components such as optical waveguides, couplers, resonators, photodetectors, etc. along with electronic components on the same silicon chip to realize high-bandwidth, high-density, and low-power communication via wavelength-division multiplexing (WDM). This talk will address the challenges of modeling and simulating silicon photonics WDM transceivers in SystemVerilog, which contain photonic devices for… Modeling and Simulation of Silicon Photonics Systems in SystemVerilog
12 events found.