Chiplets: Building the Future of SoCs

This Keynote is presented by Shankar Krishnamoorthy, General Manager, EDA Group, Synopsys

Artificial intelligence and silicon proliferation are shaping a new era of pervasive intelligence. At the forefront is the shift to multi-die, driving the advancements of trillion-transistor systems and the march to angstroms. With its promise to enable significant compute performance, heterogenous integration is a critical requirement in today’s AI-driven world. Join Shankar Krishnamoorthy, the General Manager of Synopsys’ EDA Group, as he explores the opportunities presented by multi-die design.

This Keynote is presented by Ramin Farjadrad is the founding CEO of Eliyan.

Compute performance demand has been growing exponentially in recent years, and with the advent of Generative AI, this demand is growing even faster. Moore’s law coming to an end as well as the Memory Wall (memory bandwidth & capacity) and IO Wall are the main performance bottlenecks. The chiplet system-in-package (SiP) is the industry’s solution to these bottlenecks. Silicon interposers are industry’s main technology to connect chiplets in SiPs, but they introduce several new bottlenecks. The largest interposer going to production is 2700mm2, which is ~1/4 the largest standard package substrate. Thus, a SiP with silicon interposer has limited compute & memory chiplets, thus limited performance. This presentation introduces Universal Memory Interface (UMI), a high bandwidth efficient D2D connectivity technology between XPU-Memory & XPU-XPU, which enables innovative architectures that help remove Memory & IO walls for next generation AI, specifically Gen AI, systems.

This Panel Discussion with industry experts is moderated by Nitin Dahad, Editor-in-Chief, Embedded.com.

What is the current state of the commercial chiplet ecosystem, and is a multi-company open ecosystem needed for chiplets to achieve their full potential? As we move from single company effort to a complex, multi-supplier ecosystem, we’ll discuss the biggest challenges we face, including the need to manage and reduce supply chain complexity, and doing so at reasonable cost. We’ll also talk about some of the practicalities. Do we have sufficient standards in place to enable the chiplet economy, and is there appetite for industry and vendors to collaborate on these standards? Who takes ownership of the process when chiplets come from multiple suppliers, and who is responsible for overall yield? And how do we ensure that all parts of the supply chain make money, including smaller companies and startups?

Panelists:
– Ramin Farjadrad , founding CEO, Eliyan
– Mohit Gupta, Senior Vice President, Alphawave Semi
– Nick Ilyadis, Vice President of Product Planning, Achronix
– Kenneth Larsen, Product Management Director, EDA Group, Synopsys

Presented by Letizia Giuliano, Vice President, Alphawave Semi

In this presentation, we will explore the benefits of adopting UCIe-enabled chiplet IP subsystems, featuring state-of-the-art Multi-Standard SerDes I/O connectivity for advanced AI solutions. As the need for more powerful compute capability continues to grow, the landscape and role of chiplets has become increasingly crucial for providing essential avenues for scalability, efficiency, and innovation in the infrastructure of next-generation AI data networks. We will review the obstacles associated with developing an interoperable 112G Multi-Lane and Multi-Standard I/O chiplet, and share detailed implementation insights and outcomes from Alphawave Semi’s Chiplet portfolio. Furthermore, we will demonstrate how AI connectivity use cases can be rapidly enhanced through the deployment of I/O Chiplets, which are vital for today’s multi-Terabit I/O systems. The presentation will conclude with a discussion on the challenges facing the industry and propose solutions for advancing scale-up and scale-out connectivity options to meet the networking bandwidth demands of future AI systems.

Presented by Kash Johal, CEO and Founder, YorChip

Today, Chiplets are primarily being deployed by MegaCap companies due to economics, long lead-times, and the complexity of development. QuickLogic and YorChip present a solution to deploy re-usable off-the-shelf Chiplets for everyone. Our solution empowers engineers at companies of any size to leverage chiplets:
– Modular Chiplets: Ease connectivity and enable reuse across diverse customer designs.
– Patented PHY: Supports both advanced and standard packaging, lowering development cost and production deployment.
– Legacy-Node PHY: Extends chiplet benefits to mix older process nodes (up to 90nm) with advanced nodes.
– Routing Link Layer: Reduces Latency and helps eliminate signal integrity challenges.
– AI Friendly: Chiplets specifically optimized for running Generative AI models at the edge.

The QuickLogic and YorChip collaboration empowers engineers at any size company to deploy chiplets for any application quickly and at low cost.

Presented by John Park, Product Director, Cadence

What challenges will you face when pivoting from monolithic IC design to 3D heterogenous package design? How can electronic design automation (EDA) address these challenges? As we go from Moore’s Law to More-than-Moore, technologies begin to converge across IC and systems design. This shift requires new advanced design flows combining EDA tools. These system-level design flows must enable seamless cross-domain co-design and analysis. The days of IC and package designers “throwing data over the wall” are over. Heterogeneous integration presents a new era of electronic product design with collaboration at its core – one that depends on the seamless interaction between analog/digital IC teams and package design teams. The use of advanced packaging technologies to combine smaller, discrete chiplets into one SiP not only pushes the need for more advanced multi-die packaging, but also makes packaging part of the process. This significantly reduces dependence on Moore’s Law at a time when building advanced monolithic SoCs is no longer the best option from a cost and technology perspective.

Presented by Tony Mastroianni, Advanced Packaging Solutions Director, Siemens EDA

Heterogeneous integration itself isn’t new, but new design and manufacturing technologies, combined with new product demands from system integrators, means that heterogeneous integration and 3DIC are now becoming a necessity in mainstream design. This shift however is not without its challenges as 3D IC is not a simple extension of existing packaging solutions but creates a whole new set of Multiphysics integration considerations. The interaction of thermal, mechanical, reliability, test, and core semiconductor design increases complexity and requires disparate domains to seemly collaborate.In this presentation we will explore the challenges introduced by 3D IC, the current state of the industry to address those challenges, the ecosystem needed to support 3DIC, and how users today can successfully adopt 3D IC leveraging new solutions, workflows, and 3D IC Design Kits (3D K) from Siemens EDA that are designed specifically with 3D IC in mind.

Presented by Dave Lazovsky, CEO, Celestial AI

With the growth in GenAI, AI infrastructure is not just about the System on Chip but about the System of Chips. The bottleneck is no longer compute performance of a single XPU but scale-up interconnect bandwidth, memory bandwidth and capacity. Photonic Fabric is the next generation optical interconnect technology offering >10X more performance than any competitive technology. Chiplets based on the Photonic Fabric and incorporating D2D interfaces like UCIe, MAX3 etc are built in TSMC 5nm process and are fully compatible with standard 2.5D packaging flows for easy integration with XPUs. This enables XPUs to have optical interconnects for compute-to-compute and compute-to-memory fabrics that deliver Tbps bandwidth with nano-second latencies. XPUs can also seamlessly integrate with Photonic Fabric based memory solutions offering TBs of memory capacity at full HBM3 bandwidth. This innovation empowers hyperscalers to optimize the number of XPUs needed for training & inference, improving the efficiency and economics of AI processing with significantly lower TCO2 impact.

Presented by Jun Kawaguchi, Marketing Executive, Winbond

This presentation describes the issues relating to authenticity of individual chiplet and how to ensure the supply chain security is assured. A secure supply chain is becoming increasingly critical topic to counter cybersecurity concerns and the operation of critical systems such as infrastructure systems and autonomous vehicle application. There are trusted certification organizations that will audit and assure the supply chain to be intact, however this becomes complex as multiple chiplets enter the supply chain. We will discuss these issues in the context of certified, secure memory product that Winbond provides.

Presented by Aaron Fellis, Corporate Vice President, Lam Research

As artificial intelligence (AI) continues to permeate diverse sectors, from autonomous vehicles to healthcare, there is increasing demand for more powerful and efficient AI chips. This has led to a paradigm shift, with a focus not only on the performance of AI chips but also on their packaging. As the demand for higher processing power and energy efficiency grows, advanced packaging becomes more essential to support these requirements, driving sophisticated processes and equipment technologies that can handle the complexity of packaging AI chips. The presentation will shed light on equipment innovations and packaging methodologies that are shaping the future of AI chip technology.

This Keynote is presented by Lalitha Immaneni, VP of Semiconductor R&D, Intel

With the arrival of ChatGPT, Large Language Models (LLMs) have transformed AI into an interactive and accessible technology that recursively builds on its prior accomplishments, fueling a new gold rush era of applications. AI models have exploded in complexity and size, exerting demand pressure on both compute and memory. Over time, Moore’s law has yielded a roughly 2x increase in compute every 2 years, compared to the enormous 750x per year growth demand from the LLMs. Memory is an even trickier problem as it needs to address capacity, speed and cost of data transport. Packaging plays a pivotal role in this era, architecting bespoke solutions for a highly differentiated set of applications. We take a look at the role of disaggregation, chiplets and interconnects in enabling the future of AI and HPC and illustrate this with solutions that can help create unique functionality, performance, and cost while enabling reuse and modularity.

This Keynote is presented by David Glasco, Vice President, Compute Solutions Group, Cadence.

Explore the chiplet journey and gain insights into the reasons behind the increasing adoption of chiplets and the vital role that partners play in helping engineers succeed in their chiplet journey.  Learn how the right IP portfolio and IP teams can deliver on this journey with multiple engineering engagement models and strong industry partnerships.  See how design automation flows can help accelerate product time-to-market and reduce engineering costs. Understand how the design process can be automated and how virtual platforms and package design flows can significantly improve the engineering efficiency of chiplets. Join this keynote to discover the advantages and future potential of chiplets and how partners can help you succeed.

This Keynote is presented by Sambit Sahu, Senior Vice President at Krutrim, an Ola company.

There is a huge surge in AI and HPC supercomputing currently and this will continue to accelerate. Generative AI explosion and associated multi-trillion dollar impact to revenue is triggering huge innovations in the AI space. HPC computing is on a rapid growth path with multiple supercomputers (multiple chips interconnected with high bandwidth and highly reliable network fabric and infrastructure) being built worldwide. Chiplets, which are small pieces of silicon dies targeting a particular functionality, are evolving rapidly as a concept and implementation style. In this presentation, we will talk about how chiplets are going to address some of the key challenges of building next generation AI and HPC supercomputers. We will also demonstrate the significant economic advantages of chiplets architecture over conventional monolithic architectures. We will also demonstrate methodologies and approaches on how to use chiplets for your cost advantage. We will walk through how we are capitalizing on the chiplet strategy for economic advantage in building our high end AI server, scaling upto a supercomputer. We will walk through strategies in optimizing NRE costs, optimizing TCO, optimizing on scaleout costs, and optimizing on time to market, and extending the benefits to additional products.

Technical Talk with Michael Munsey, Vice President, Siemens EDA and Sally Ward-Foxton, Senior Reporter, EE Times

Semiconductor sustainability starts with design and the decisions made during the design process affect sustainability. This is amplified as we transition to the heterogeneous integration of chiplets using advanced substrate platforms such as 2.5/3D in order to continue silicon scaling. By linking the digital twins for semiconductor design to the digital twin of a semiconductor fab, design details can be fed forward to optimize fabs for sustainability and manufacturing data can be fed back to optimize design libraries and decisions. In this talk, we will talk about the evolution of the digital twin, how new solutions aid design and manufacturability, and the start of a new semiconductor era.

This Panel Discussion with industry experts is moderated by Sally Ward-Foxton, Senior Reporter, EE Times.

Chiplets are attracting a lot of attention, but which industries or verticals will benefit most from chiplets in the short term, and why? We’ll start by talking about applications for chiplets and how they will evolve as the technology matures.We’ll discuss the biggest challenges to designing successful multi-die systems today. How do we ensure dies from different processes work together, and what about dies designed by different companies? Are standards ready for this challenge, and how are design tool vendors, silicon vendors and IP providers taking it on? We’ll cover topics like multi-die system simulation, emulation and verification, and whether the complexity of these processes is limiting the size and scope of multi-die designs today.

Panelists:
– David Glasco, Vice President, Compute Solutions Group, Cadence
– Andreas Olofsson, CEO, Zero ASIC
– Sambit Sahu, Senior Vice President, Krutrim, an Ola company
– John Sotir, Senior Director, Altera, an Intel Company

This Keynote is presented by Andreas Olofsson, CEO and founder of Zero ASIC.

The compounding effect of monolithic miniaturization on electronics has been nothing short of miraculous. Fifty plus years of Moore’s Law has resulted in a million fold improvement in computing cost and efficiency. Now that physical device scaling is approaching hard atomic limits, the question is: Where will the next million fold computing efficiency improvement come from? Extreme domain specific circuit specialization can provide the next 1,000 bost, but the path is blocked by the prohibitive cost and complexity of ASIC design. Chiplets offer a compelling solution to reducing the cost and time of ASIC design, but challenges remain. In this talk, I will present my experience with chiplets over the last decade, review the current obstacles, and propose some potential paths for the future.

This Tutorial is presented by Dr. Tony Chan Carusone, Chief Technology Officer, Alphawave Semi

In this tutorial, Tony Chan Carusone, CTO of Alphawave Semi, explores the crucial advancements required to propel the next generation of computing, with a particular emphasis on AI as a transformative force reshaping our daily lives and data management systems. He highlights how pervasive connectivity, from extensive optical fiber networks to intricate chiplet wirings, is critical for AI functionalities. The discussion traces AI’s evolution over the last two decades. These developments are pivotal in meeting the computational demands, from teraflops to petaflops, while focusing on sustainability through chiplet-based designs. Additionally, he will delve deeper into the chiplet architecture, discussing how it revolutionizes cost and power efficiencies in AI applications. Tony will detail Alphawave Semi’s leadership in providing connectivity solutions specifically designed for chiplet architectures, including the groundbreaking UCIe interface that offers a path up to 10 Tbps/mm bandwidth density. The session will further examine how AI is transforming data infrastructure connectivity, highlighting the necessity for robust inter-chip links within datacenters and the reengineering of optical networks that cater to AI’s specific needs. The session wraps up by addressing the trend toward disaggregated computing and distributed data centers, facilitated by low-latency connectivity.

Presented by Durgesh Srivastava, Chief Technology Officer, MIPS

Compute requirements have outpaced supply by 10x. Historically, HW advancements consistently outpaced SW. However, the advent of GenAI has reversed this trend, with SW developments now outstripping HW. Advanced algorithms, especially those involving deep learning and large-scale data processing, require vast processing power, memory, and efficient data handling. The computational demands of training and running GenAI models have pushed traditional silicon-based processors to their limits, necessitating new hardware designs. Concurrently, the slowdown of Moore’s Law has worsened these challenges. The chiplet architecture has emerged as a promising solution. This presentation will discuss how MIPS’ data-centric approach, with the integration of the RISC-V ISA, is driving the chiplet revolution, optimizing data flow and processing efficiency to bridge the HW-SW gap and ensure ongoing computational advancements.

Presented by Dr. Yervant Zorian, Chief Architect and Fellow, Synopsys

This technical presentation discusses four multi-die health management solutions for different chiplet-to-chiplet configurations: Using IEEE 1838 for testing interconnects and dies (or chiplets) in a GPIO-based configuration, using Synopsys SLM SMS EXT-RAM for test and repair of interconnects and DRAMs in an HBM-based logic-to-memory chiplet configuration, using MTR for monitoring, test, and repair of interconnects in a UCIe-based chiplet-to-chiplet configuration, using lane test and repair (LTR) for monitoring, test, and repair of light I/O in a TSV-based hybrid bonding configuration.

Presented by Jeff Twombly, VP Business Development, Credo

This presentation will cover critical SerDes IP development, chiplet productization, testing considerations to enable volume at scale, and how Credo’s experience and infrastructure will enable more chiplet variants required for emerging I/O standards such as UCIe. Credo is a proven industry leader in providing high-performance, low power chiplet solutions. Credo has two 3.2Tbps chiplets shipping in production. Credo developed all the necessary IP inhouse and combined our purpose built SerDes blocks to create the chiplet products. The 3.2Tbps Nutcracker device utilizes 32-lanes of 112G XSR SerDes to connect to the ASIC/SoC die and 32-lanes of 112G MR SerDes for the off-package, line-side connectivity. The XSR interface can connect up to 50mm trace lengths on standard organic packaging substrates. The 3.2Tbps BlueJay device was developed to enable multi-chip module solutions using TSMCs CoWoS, InFO, and/or SoIC 3DFabric configuration technology. Credo developed a BoW (bunch of wires) interface to connect to the ASIC/SoC die and enables the off-package, line-side connectivity with 64-lanes of 56Gbps LR SerDes.

Presented by Deepak Shankar, Founder and Chief Visionary, Mirabilis Design

Design of chiplet architectures must transition from silicon-centric to system-centric. Early application-specific architecture exploration provides power, latency, throughput and thermal impact statistics to measure quality and efficiency. The exploration covers partitioning of heterogeneous compute resources onto chiplets, task assignment, maximize throughput and minimize latency, manage power and thermal below the threshold for corner cases, and scalability across workloads and tasks. System modeling using IP blocks enables this using multi-abstraction methodology with rapid modeling, extensive exploration with constraints and optimization of the specification. During the session, we will explain the exploration of real-life examples using system modeling. How to determine the best assignment of caches and memory at the host processor vs chiplet hub vs accelerator? How do you ensure chiplets are of the same dimension and thermal is equally distributed? How do you decide between UCIe standard vs advanced, number of UCIe interfaces, memory request distribution and coherency on performance?