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Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can be a bottleneck in the project cycle due to its complexity. The nature of a GLS can cause simulations to run much longer than the… Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
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Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices
Learn How STMicroelectronics Silicon Carbide (SiC) Research Team uses Silvaco TCAD to Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices During SiC device switching operations, it is possible that devices could be reaching abnormal overload conditions, which is why some applications require “robustness” specifications (e.g., Short Circuit and UIS… Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices
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High-Performance RTL Simulation Workflow with Quartus and Active-HDL
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs).… High-Performance RTL Simulation Workflow with Quartus and Active-HDL
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RISC-V Instruction Set Architecture: Enhancing Computing Power
*Work email required for registration* Don't miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that promises to inspire and inform: - Gain insights into the latest trends shaping chip design. - Learn from industry leaders about the strategies behind successful… RISC-V Instruction Set Architecture: Enhancing Computing Power
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Siemens EDA User2User Conference
Santa Clara Marriott 2700 Mission College Blvd, Santa Clara, CA, United StatesEngineer a smarter future, faster at Siemens EDA User2User Conference April 3-4, 2024 Santa Clara, CA. Join your colleagues from around the industry for a day of technical sessions, networking, keynote sessions, labs and more. User2User is free of charge for Siemens EDA customers and includes sessions, lunch, and parking. Technology tracks covering the latest… Siemens EDA User2User Conference
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ISQED Symposium 2024
Seven Hills Conference Center 800 Font Blvd, San Francisco, CA, United StatesA pioneer and leading interdisciplinary conference, the 25thInternational Symposium on Quality Electronic Design (ISQED'24) accepts and promotes original and unpublished papers related to the topics shown below. ISQED'24 theme is AI/ML& Electronic Design, Hardware Security, Quantum Computing, 3D Integration, and IoT. Authors are invited to submit papers in following topics (please visit the website for… ISQED Symposium 2024
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Maximizing the Benefits of Virtuoso Layout Suite XL
Find out how the Virtuoso Layout Suite XL you’ve known for many years is setting new standards in custom layout authoring. The connectivity-driven paradigm keeps the layout in synch with the circuit design and ensures that the design intents are always honored. Learn how we strengthened the layout editor in Virtuoso Studio, launched in 2023,… Maximizing the Benefits of Virtuoso Layout Suite XL
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Hierarchical Analysis of EM Crosstalk with EMX Planar 3D Solver
Identifying sources of electromagnetic (EM) coupling and safeguarding today’s complex electronic designs from EM crosstalk are daunting tasks. For designs with multiple levels of hierarchy, identification, and detailed analysis of the “EM-sensitive” content is a challenge. The manual creation of wrapper cells or new layout views to enable this quickly becomes a time-consuming and error-prone… Hierarchical Analysis of EM Crosstalk with EMX Planar 3D Solver
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High-Performance RTL Simulation Workflow with Libero and Active-HDL
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs).… High-Performance RTL Simulation Workflow with Libero and Active-HDL
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Guiding your aerospace electrical journey
Aerospace electrical/electronic (EE) design requires a delicate balance between innovative technology and uncompromising reliability. Meanwhile, the pressure to get products to market faster is growing exponentially. Finding ways to design electrical systems quickly, cost-effectively and efficiently has become a central focus of manufacturers. Siemens has the solutions and partnerships to guide the development of best-in-class… Guiding your aerospace electrical journey
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Ansys 2024 R1: High Frequency Electronics What’s New
Learn about the latest improvements and new features to the high frequency electronics simulation tools. There are many enhancements for engineers involved in RF, automotive, A&D, and consumer electronics designs that our subject matter experts will discuss. Overview This Ansys 2024 R1 webinar will review the high-frequency electronics tool updates, enhancements, and new features –… Ansys 2024 R1: High Frequency Electronics What’s New
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Embedded World 2024
NürnbergMesse Messezentrum 1, Nurnberg, GermanyThe embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community, including leading experts, key players and industry associations. It offers unprecedented insight into the world of embedded systems, from components and modules to operating systems, hardware and software design, M2M communication, services, and various issues related to… Embedded World 2024
12 events found.