RISC-V Instruction Set Architecture: Enhancing Computing Power

*Work email required for registration*

Don’t miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that promises to inspire and inform:

– Gain insights into the latest trends shaping chip design.

– Learn from industry leaders about the strategies behind successful SoC design.

– Discover how RISC-V and software-defined products are shaping the future of chip architecture.

– Network with professionals and experts in the field.

Software Defined Products: Meeting the Challenges of Change

Andes Technology Corp.

Presenter: Bing Yu, Computer and AI Architect, Andes Technology USA Corp. The adoption of the RISC-V instruction set architecture has revolutionized chip design. For the first time, designers can extend the instruction set architecture to achieve significant improvements in performance or reductions in power consumption. Bing Yu will delve into how this trend has propelled Andes Technology Corp. to success.

Menta SAS

Presenter: Gareth Baron, Applications Engineering Director, Menta SAS North America. As the industry moves towards software-defined products, there’s an increasing demand for flexibility in chip design, including the flexibility to update some portions of the logic post-fab. Gareth Baron will explore this trend, drawing from examples like Software Defined vehicles. Learn how Menta SAS has navigated the challenges of designing for change in silicon.

*This webinar is in partnership with SemiWiki, Andes, and Menta SaS*