-
Navigating Trends and Tools in Automotive Design with Cadence
Join us for our first webinar in this insightful series, where we explore the rapidly evolving automotive landscape. We will focus on the rise of autonomous and electric vehicles, highlighting key trends such as ADAS, software-defined vehicles, and zonal architectures. Learn how Cadence’s advanced automotive solutions are addressing the increasing compute demands and in-vehicle networking… Navigating Trends and Tools in Automotive Design with Cadence
-
Phil Kaufman Award & Banquet
Hayes Mansion 200 Edenvale Avenue, San Jose, CA, United StatesThe Phil Kaufman Award honors individuals who have had a demonstrable impact on the field of electronic system design through technology innovations, education/mentoring, or business or industry leadership. The award was established as a tribute to Phil Kaufman, the late industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers. Electronic System… Phil Kaufman Award & Banquet
-
Navigating COTS-IP in DO-254: Strategies for Safe and Efficient FPGA Design
The integration of COTS-IP (Commercial Off-The-Shelf Intellectual Property) components in FPGA-based Avionics systems can significantly speed up development and enhance performance. However, it also introduces unique challenges, as these components may not align with the strict aviation development assurance standards required for DO-254 compliance. This webinar will guide you through the process of balancing the… Navigating COTS-IP in DO-254: Strategies for Safe and Efficient FPGA Design
-
APCCAS 2024
Chang Yung-Fa Foundation No. 11, Zhongshan S. Rd., Taipei City, TaiwanThe APCCAS is a major international forum for researchers, scientists, educators, students and engineers to exchange their latest findings in circuits and systems. It covers a wide range of topics including, but not limited to the following： Artificial Intelligence Circuits, Systems, and Applications Digital Integrated Circuits and Systems Analog and Mixed Signal Circuits and Systems… APCCAS 2024
-
IEEE World Technology Summit – AI INFRASTRUCTURE
San Jose Convention Center 150 W San Carlos Street, San Jose, CA, United StatesThis event features top executives from around the world who describe the burning issues surrounding AI and how to solve our immediate problems, focusing on these core areas: AI applications and their required infrastructure Silicon to support AI applications Systems to support AI applications Security and Standards AI is critical to our future. Please join… IEEE World Technology Summit – AI INFRASTRUCTURE
-
Rise Together Beyond RTL : Practical Techniques for Improving ASIC Design Efficiency and Early Verification
High-level design techniques and automation tools to address the limitations of traditional RTL, reduce verification times, improve performance, and manage growing design complexity—integrating seamlessly. What You'll Learn: This Lunch & Learn offers an in-depth look at Rise Design Automation tools and illustrates how high-level design and early verification techniques can bring value to your projects.… Rise Together Beyond RTL : Practical Techniques for Improving ASIC Design Efficiency and Early Verification
-
ASIP University Day 2024: Domain-Specific Processor Design using ASIP Designer
The AI revolution and other application domains, like data centers, advanced wireless communications, image and video processing, automated driving assistance, and post-quantum cryptography need more powerful architectures with higher performance. This is driving demand for heterogeneous multicore systems including application specific instruction set processors (ASIPs). ASIPs have become a mainstream implementation option for modern SoCs,… ASIP University Day 2024: Domain-Specific Processor Design using ASIP Designer
-
Tessolve AI Strategy & Eco System for DV
With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification, Tessolve has been working on improving internal DV processes, with impressive reductions in both effort and costs, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short… Tessolve AI Strategy & Eco System for DV
-
AI-Driven Constraint Generation for PCB and IC Package Design
Join our webinar to discover how AI-driven optimization and automation in constraint generation can boost productivity and shorten design cycles for PCB and IC package design. Learn how integrating Allegro X and Sigrity X can streamline your workflow. Key Takeaways: Learn how the Sigrity Topology Workbench, a robust system-level SI/PI environment for what-if and pre-route… AI-Driven Constraint Generation for PCB and IC Package Design
-
Optimize Systems and Semiconductor Architecture for Deep Learning Algorithms Using System-Level Modeling
In a world where artificial intelligence and machine learning are embedded in critical applications—from real-time tracking and object detection to autonomous systems—the architecture behind these innovations must be both powerful and efficient. To help engineers and architects address these challenges, our upcoming webinar will demonstrate how System-Level Modeling can be a game-changer in optimizing the performance and… Optimize Systems and Semiconductor Architecture for Deep Learning Algorithms Using System-Level Modeling
-
Workshop on Open Source EDA Technologies (WOSET)
Virtual! No registration fee! The WOSET workshop aims to galvanize the open-source EDA movement. The workshop will bring together EDA researchers who are committed to open-source principles to share their experiences and coordinate efforts towards developing a reliable, fully open-source EDA flow. The workshop will feature presentations and posters that overview existing or under-development open-source… Workshop on Open Source EDA Technologies (WOSET)
-
2024 TSMC Europe OIP Ecosystem Forum
Hilton Amsterdam Airport Schiphol Schiphol Boulevard 701 Amsterdam, Amsterdam, NetherlandsLearn About: Emerging advanced node design challenges and corresponding design flows and methodologies for A16, N2 and N3 processes Latest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes, InFO, CoWoS®, and SoIC, 3DFabric Alliance, and 3Dblox™ standard, plus innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile applications Comprehensive design… 2024 TSMC Europe OIP Ecosystem Forum
12 events found.