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DVClub Europe – September 2024
This DVClub event will have talks on verification of low power features of VLSI designs, discussing strategies for accurately measuring power consumption and ensuring that power-saving mechanisms are effective. Additionally, speakers will share insights on how to simulate and analyze different power scenarios to identify potential issues and optimize power management techniques. Attendees will have… DVClub Europe – September 2024
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Elevate Your Analog Layout Design to New Heights
Are you ready to transform your career and become a master of analog layout design? Look no further than The Advanced Analog Layout Course! This course is meticulously crafted to enhance your physical design skills, guiding you through the advanced techniques essential for creating top-notch, well-matched, and noise-resistant layouts on a CMOS process. Learn Anytime, Anywhere! Our course is delivered through a user-friendly… Elevate Your Analog Layout Design to New Heights
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Hardware-Accurate Digital Twins in Defense: Case Study
The defense industry is increasingly seeking innovative approaches to accelerate system development while ensuring reliability. Hardware-accurate digital twins offer a promising solution. This webinar will explore the concept of hardware-accurate digital twins and their application in defense. Join Cadence and Northrop Grumman as we delve into a real-world case study demonstrating the power of digital… Hardware-Accurate Digital Twins in Defense: Case Study
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Synopsys Processor IP Summit 2024: RISC-V, DSP and NPU IP for Your Diverse SoC Processing Needs
Santa Clara Marriott 2700 Mission College Blvd, Santa Clara, CA, United StatesAs electronic systems continue to become more complex and integrate greater functionality, SoC developers are faced with the challenge of developing more powerful, yet more energy-efficient devices. The processors used in these applications must be efficient to deliver high levels of performance within limited power and silicon area budgets. Why Attend? Join us for… Synopsys Processor IP Summit 2024: RISC-V, DSP and NPU IP for Your Diverse SoC Processing Needs
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Enhanced Packaging Performance and Manufacturing with Physics-Based 3D Simulation
About this webinar Digital engineering is ramping up across the CPG, healthcare and wider packaging sector. Packaging engineers are tasked with producing fit-for-purpose packaging that is optimised for customer-use, transportation, storage and for production-line filling/handling. In addition, manufacturing the packaging containers as optimally as possible to avoid defects is vitally important. All in the landscape… Enhanced Packaging Performance and Manufacturing with Physics-Based 3D Simulation
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Using OSVVM’s AXI4 Verification Components
Abstract: This “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 2 of this presentation focuses on how to write tests and configure the AXI4 VCs. AXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity is due to the… Using OSVVM’s AXI4 Verification Components
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MLCAD Symposium 2024
Snowbird 9385 Snowbird Center Trail, Sandy, UT, United StatesThe symposium focuses on Machine Learning (ML) for all aspects of CAD and electronic system design. The symposium is sponsored by both the ACM Special Interest Group on Design Automation (SIGDA) and the IEEE Council on Electronic Design Automation (CEDA). The symposium program will have keynote and invited speakers in addition to technical presentations. MLCAD… MLCAD Symposium 2024
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AI Hardware & Edge AI Summit 2024
Signia by Hilton 170 S Market Street, San Jose, CA, United StatesThe AI Hardware & Edge AI Summit is the ultimate destination for the entire AI and ML ecosystem, with a collaborative mission to train, deploy and scale machine learning systems that are fast, affordable, and efficient. Whether it’s forging new partnerships, staying ahead of the ever-changing semi-conductor landscape, learning how to build, train, and deploy efficient systems,… AI Hardware & Edge AI Summit 2024
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IP-SoC South Korea 24
EL Tower 6F 213 Gangnamdaero, Seoul, Korea, Republic ofA worldwide connected Event !! D&R IP-SoC South Korea 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight their latest products and services and share their vision about the next innovation… IP-SoC South Korea 24
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Can AI make cameras see in the dark?
Abstract As cameras become ubiquitous in applications such as surveillance, mobile, drones, and automotive systems, achieving clear vision 24/7 under any condition—including extreme low light and high dynamic range scenarios—has become essential. By leveraging Edge AI processors, a software ISP based on neural network technology can process and optimize video in real-time, surpassing human… Can AI make cameras see in the dark?
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Faster Design TAT and Upscaled Team Productivity with Cadence’s True Hybrid Cloud
Join us for an informative webinar as we unveil the new hybrid cloud capabilities of our cloud solutions designed to revolutionize EDA workloads. Whether you need peak capacity for a short duration or want a front-to-back turnkey cloud environment, our cloud solutions offer unparalleled flexibility and efficiency. We will discuss how Cadence True Hybrid Cloud… Faster Design TAT and Upscaled Team Productivity with Cadence’s True Hybrid Cloud
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Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs
Delve into how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation. The solution integrates comprehensive protocol knowledge and provides user-friendly interfaces, significantly reducing the setup time for verification environments. Optimized for top-tier performance and scalability, Questa Formal VIP… Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs
12 events found.