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Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs
September 11 @ 8:00 am - 9:00 am PDT
Delve into how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation. The solution integrates comprehensive protocol knowledge and provides user-friendly interfaces, significantly reducing the setup time for verification environments. Optimized for top-tier performance and scalability, Questa Formal VIP AMBA is the ideal tool for achieving high-efficiency and accurate protocol compliance. Don’t miss this opportunity to learn how to streamline your verification process and enhance your design workflows.
What You Will Learn:
- Challenges in IP Integration
Understand the common obstacles faced by designers and verification teams during IP integration and how to overcome them. - Benefits of Formal Verification Ips
Discover the advantages of using formal verification IPs, including enhanced accuracy and reduced need for simulation. - Capabilities and Supported Protocols
Explore the extensive capabilities of Questa Formal VIP AMBA and the range of protocols it supports. - From Specification to Formal Properties
Learn how protocol specifications are transformed into formal properties for effective verification. - Debugging Protocol Violations
Gain insights into debugging techniques for protocol violations to ensure compliance and reliability.
Who Should Attend:
- RTL Design Engineers
- Design Integrators
- Design Verification Engineers
What/Which Products are Covered:
- Questa Formal VIP AMBA
- Questa Formal VIP OnChip
- Questa Check Register
Nicolae Tusinschi is a product manager for formal verification solutions at Siemens EDA. He holds a master’s degree combined between the University of Southampton and the University of Kaiserslautern. After a master’s thesis at Continental, Nicolae joined OneSpin, where he worked in QA, then as a product specialist and later served as product owner for design verification tools at OneSpin. His key projects include integrating simulation coverage with formal metrics, leveraging coverage results in the verification process, formal verification of RISC-V cores.