Cadence Managed Cloud for Cost Efficient and Productive Chip Design
Join us for an informative webinar, as we unveil the capabilities of our cloud solutions designed to revolutionize EDA workloads. Whether you require completely hosted environments or need peak/burst capacity, our cloud solutions offer unparalleled flexibility and efficiency. We will discuss how Cadence Managed Cloud can optimize cost-efficiency and productivity for your chip design projects.… Read More »Cadence Managed Cloud for Cost Efficient and Productive Chip Design
Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim
Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process. Learn how the latest innovations in QuestaSim address these challenges by enabling full off-line… Read More »Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim
DVClub India – Ensuring my Design Verification is ISO26262 Compliant
Cadence, Bengaluru Sarjapur Outer Ring Road, Bengaluru, IndiaTBD
Exploring the Advancement of Chiplet Technology and the Ecosystem
Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent article from the Financial Times, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth, manufacturers recognize the… Read More »Exploring the Advancement of Chiplet Technology and the Ecosystem
CadenceLIVE Silicon Valley 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesJoin us for CadenceLIVE Silicon Valley 2024 on April 17 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings users, developers, and industry experts together to connect, share ideas, and inspire design creativity. Attendees have the opportunity… Read More »CadenceLIVE Silicon Valley 2024
Latch-Up 2024: Boston
Massachusetts Institute of Technology 77 Massachusetts Avenue, Boston, MA, United StatesFriday to Sunday April 19–21, 2024 in Boston, MA, USA The Latch-Up conference is a weekend of presentations and networking dedicated to free and open source silicon. It's an event for the open source digital design community, much like its European sister conference ORConf, run by the FOSSi Foundation. You are all invited! The FOSSi… Read More »Latch-Up 2024: Boston
42nd VLSI Test Symposium
Memorial Union Conference Center 1151 S Forest Ave, Tempe, AZ, United StatesThe IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in test, validation, yield, reliability, and security of microelectronic circuits and systems. The symposium will take place on April 22-24 2024, in Tempe, AZ, USA. The program includes keynotes, scientific paper presentations, short industrial application paper presentations, special sessions, and Innovative Practices sessions.… Read More »42nd VLSI Test Symposium
TSMC 2024 Technology Symposium – North America
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesLearn about: TSMC's industry-leading HPC, smartphone, IoT, and automotive platform solutions TSMC’s advanced technology progress on 5nm, 4nm, 3nm, 2nm processes and beyond TSMC’s specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and more TSMC 3DFabric™ advanced packaging technology advancement on InFO, CoWoS®, and TSMC-SoIC® TSMC’s manufacturing excellence, capacity expansion… Read More »TSMC 2024 Technology Symposium – North America
TechNES FPGA Front Runner Event
New Mills Wotton-under-Edge, United KingdomThe FPGA Front Runners event will be hosted by Renishaw at their venue in Wotton-under-Edge. The event will focus on “Using AI in development and product for FPGA”. If you are interested in speaking at this event please email mike.bartley@techworks.org.uk Topics for talks: What AI support is being built into the FPGA fabrics? How are… Read More »TechNES FPGA Front Runner Event
Ansys – Simulation World 2024
Did you know that simulation helped Pratt & Whitney design a game-changing engine architecture that has saved aircraft operators over a million gallons in fuel? Or that sustainable energy start-up Amogy is using simulation to build a novel, portable, carbon-free energy system to convert ammonia into renewable fuel that will power green transportation solutions of the future? Or that… Read More »Ansys – Simulation World 2024
AI-Driven EM-IR Design Closure
IR drop closure is becoming a major challenge for designers on advanced nodes. The number of violations at signoff has increased significantly, leading to longer turnaround time (TAT) or violations being waived. To solve this challenge, IR drop needs to be addressed early in the implementation phase with an automated IR prevention and fixing methodology.… Read More »AI-Driven EM-IR Design Closure
Embedded Vision Summit 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesThe Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems, cloud solutions and mobile applications. Why Attend? It's a First-Rate Program with Powerful Insights into Practical Perceptual AI. Join us for three days of learning—from tutorials to Deep-Dive Day, covering the latest technical insights,… Read More »Embedded Vision Summit 2024