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Silvaco UseRs Global Event – USA, 2025

January 15 @ 9:00 am - 4:00 pm PST

Silvaco SURGE 2025

Silvaco will hold its annual SURGE users event on January 15, 2025. 

SURGE brings the TCAD, EDA, and IP communities together to discuss new technologies, share users’ experiences, and discover innovative techniques for advanced semiconductor design.

Everyone that registers will be entered into a drawing to win one of 2 pairs of Apple AirPods Pro 2.

All attendees will be entered into a drawing to win one Apple iPad Air 11″ M2.

AGENDA

Time General Session
9:00 AM Keynote – Babak Taheri, Chief Executive Officer and Director, Silvaco​
9:15 AM​ AI Takes EDA to the Next Level – Wally Rhines, President and CEO of Cornami and Silvaco Board Member​
9:30 AM NanoHub Workforce Development – Dr. Peter Griffin, Stanford University 
Time SEMICONDUCTOR PROCESS AND DEVICE TRACK (TCAD)
9:45 AM TCAD Update – Dr. Eric Guichard, SVP and GM of TCAD Business Unit, Silvaco​
10:00 AM​ Low-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation – Sanam Moslemi-Tabrizi, Analog Engineer, Ciena
10:15 AM​ Machine Learning for Multi-Scale Plasma Process Integration and Optimization – Associate Professor Dr. Lado Filipovic, TU Vienna
10:30 AM​ TBA – Sumeet Pandey, Micron Technologies​
10:45 AM​ Applying Artificial Intelligence in Fab Technology Co-Optimization – Dr. Christian Caillat, TCAD Senior Staff FAE, Silvaco ​
11:05 AM​ Developing Silicon Carbide DMOSFETs: A Digital Twin Design Reference Flow – Dr. David Green, TCAD Applications Engineer, Silvaco
11:25 AM​ Power Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology – Dr. Bogdan Tudor, Head of Modeling, Silvaco​
12:00 PM​ LUNCH BREAK​
Time IC Design Track (EDA and IP)​​
1:00 PM EDA and IP Updates – Dan Fitzpatrick, VP and GM of EDA Business Unit, Silvaco – Ben Louie, VP and GM of IP Business Unit, Silvaco
1:20 PM EDA Solutions for Physical Design of Discrete Power Devices – Stefano Pettazzi, Staff Applications Engineer, Silvaco​
1:40 PM Jivaro Pro Advanced Parasitic Reduction – Chung-Chun Chen, Director of Analog Design, Silicon Creations ​
2:00 PM Using Viso to Investigate, Analyze and Solve Advanced Parasitics Issues – Carlos Berlitz, Corporate Applications Engineer, Silvaco
2:15 PM Standard Cells Characterization Challenges and Improvement – Siti Mariyam, IP Design Enablement, SilTerra
2:35 PM Low Voltage Standard Cell Operation at 3nm – Fernando Carrion, R&D Engineer, Silvaco
3:00 PM Advanced Node Library Development with Cello FinFET – Felipe Bortolon, Engineering Manager IP, Silvaco​
3:20 PM LDO and Bandgap References for Low Voltage Operation – Ahmad S. Mazumder, Director of Engineering, Silvaco – Shaikh A Shams, Staff Engineer, Silvaco
3:35 PM Introduction to CAN-XL, Mauricio Brochi, Director of Automotive IP, Silvaco

Agenda subject to change.

Details

Date:
January 15
Time:
9:00 am - 4:00 pm PST
Event Categories:
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Website:
Event Website

Organizer

Silvaco
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