Latest Past Events
RISC-V 101
Santa Clara Convention Center 5001 Great America Parkway, Santa ClaraThe RISC-V Instruction Set Architecture (ISA) is the future of computing. As an open standard, RISC-V is accelerating innovation and enabling unprecedented design freedom across every computing application. You've seen the headlines and stories. Now, here's your chance to learn all about RISC-V and why it is being rapidly adopted by organizations of all size… RISC-V 101
RISC-V Summit US
Santa Clara Convention Center 5001 Great America Parkway, Santa ClaraEach day, thousands of engineers around the world collaborate and contribute to advance RISC-V, the open-standard instruction set architecture that is defining the future of open computing. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly, enjoy unprecedented design freedom, and substantially reduce the… RISC-V Summit US
IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis
Cadence Design Systems, Building 5 2655 Seely Avenue, San JosePower integrity (PI) is a major challenge for chip designers in the era of ubiquitous data, hyperconnectivity, and AI. Design size is exploding, and innovations in heterogenous integration are adding to PI complexity. These changes and challenges are ushering in the IR2.0 era ― a new paradigm for power integrity design and analysis. As a… IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis