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IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis

November 2 @ 10:00 am - 5:00 pm PDT

Cadence, November 2 2023

Power integrity (PI) is a major challenge for chip designers in the era of ubiquitous data, hyperconnectivity, and AI. Design size is exploding, and innovations in heterogenous integration are adding to PI complexity. These changes and challenges are ushering in the IR2.0 era ― a new paradigm for power integrity design and analysis.

As a leading-edge chip designer, do you frequently find yourself with too many IR violations to be fixed at the signoff stage? They might require a long time to fix the violations or even waive them, increasing the turnaround time or risk of failure. To meet these challenges, we need new analysis methods like hierarchical analysis, incremental IR drop analysis, early prototyping, optimization of power networks for chiplets and 3D-ICs, as well as new methods of design coverage. In addition, we need a “shift left” strategy enabled with AI that can integrate PI in the implementation process to identify, automatically diagnose, and fix PI problems efficiently, leaving little room for surprise at signoff.

Join us at our CadenceCONNECT event and learn from technical experts in academia, foundries, the design community, and Cadence on how we are addressing these PI challenges.

The seminar is free and open to technical experts and managers involved in physical design implementation and silicon signoff. Lunch and snacks are provided.


Morning Sessions

Welcome and Opening Remarks

Machine Learning Methods for Power Delivery Network Design
Dr. Sachin Sapatnekar
Henle Chair in ECE and the Distinguished McKnight University Professorship, University of Minnesota

IR2.0 – A New Paradigm for Power Integrity Analysis and Design
Ben Gu
Corporate Vice President, Cadence

Yufeng Luo
Corporate Vice President R&D, Cadence

IR-Aware Design Flow in Advanced Nodes

Florin Dartu
Senior Technical Manager, TSMC

Afternoon Sessions

IR-Driven Implementation

Shane Stelmach Power Analysis,
Power Integrity, and Reliability Design Lead, Texas Instruments

Concurrent PI Closure Towards Predictable Design Convergence

Anand Rajagopalan
Physical Design Technical Manager, MediaTek

A Novel Hierarchical Power Integrity Signoff Methodology for Ultra Large SoCs

Rossana Liu
CAD Director, Microsoft

Power Integrity Analysis on Cloud

Gil Pedro
Amazon Web Services

Karan Sahni
Sr. Product Group Director, Cadence

3D-IC and System-Level PI Analysis

Jags Jayachandran
Solutions Architect, Cadence

Closing Remarks


November 2
10:00 am - 5:00 pm PDT
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Cadence Design Systems, Building 5
2655 Seely Avenue
San Jose, CA 95131 United States
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