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Enhance Verification Quality with the Xcelium Mixed-Signal App
The comprehensive verification of analog mixed-signal (AMS) designs has challenges in schedules and implementations due to the vast divergence in design flows of the analog and digital portions of the SoC. These discrepancies include priorities in simulation cycles (accuracy versus performance), design methodologies, and verification of functionality. Over multiple decades, design verification (DV) has evolved… Enhance Verification Quality with the Xcelium Mixed-Signal App
Synopsys: AMS SIG India – 10th Edition
Radisson Blu Outer King Road, BengaluruThe recent surge in demand for mobile, networking, edge computing and automotive chips has challenged engineers to innovate across multiple domains – power efficiency, footprint and die cost. Meanwhile, the semiconductor shortage has increased wafer costs and fabrication times, thereby shortening design cycles and making first-pass success a must-have. Shrunk time to market has pushed… Synopsys: AMS SIG India – 10th Edition
Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification
Learn how to write UVM testbenches for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes to build reusable and scalable testbenches for digital designs, and it can be extended to verifying analog circuits simply by using a fixture module that generates analog stimuli and measures analog responses with Scientific Analog's… Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification