Enhance Verification Quality with the Xcelium Mixed-Signal App

The comprehensive verification of analog mixed-signal (AMS) designs has challenges in schedules and implementations due to the vast divergence in design flows of the analog and digital portions of the SoC. These discrepancies include priorities in simulation cycles (accuracy versus performance), design methodologies, and verification of functionality.

Over multiple decades, design verification (DV) has evolved towards catching bugs earlier in the design cycles, allowing an exponential increase in the functionality of SoCs. Extending those improvements to mixed signal is critical for continuous growth. This CadenceTECHTALK goes over many of the silicon-proven approaches enabling it, and DV engineers will find immense value in the contents. Specifically, it covers solutions to those challenges in mixed-signal verification (MSV) using the capabilities of the Xcelium Mixed-Signal App.

What attendees will learn:

• Development of analog modeling in SystemVerilog using real number modeling (RNM)
• MSV co-sim testbench architecture to allow swapping of models and netlists
• Enhancements of DV regression setup with a hybrid flow that allows for both RNM and co-sim