Bluespec
3rd Workshop on Open-Source Design Automation
Flanders Meeting & Convention Center Antwerp Antwerp, BelgiumCall for papers There is no doubt that proprietary EDA tools are successful, mature, and fundamental for hardware development. However, the “walled garden” approach created by closed-source tool flows can hamper novel FPGA/ASIC-based applications and EDA innovation alike by requiring that researchers either operate within the limits of what has already been imagined, or require… Read More »3rd Workshop on Open-Source Design Automation
Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This Synopsys webinar demonstrates the verification of standard RISC-V ISA extensions. A subsequent webcast will demonstrate custom ISA verification. The multiple ISA verification problem is solved by RISCV-DV with configurability for ISA… Read More »Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study