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3rd Workshop on Open-Source Design Automation

April 17, 2023 @ 2:00 pm - 6:00 pm CEST

OSDA 2023

Call for papers

There is no doubt that proprietary EDA tools are successful, mature, and fundamental for hardware development. However, the “walled garden” approach created by closed-source tool flows can hamper novel FPGA/ASIC-based applications and EDA innovation alike by requiring that researchers either operate within the limits of what has already been imagined, or require that they attempt to simulate their effects on incomplete models, potentially leading to incorrect conclusions.

Another recent development has been growing activity in the open-source community to produce open equivalents of EDA tools, as well as efforts to document FPGA architectures. For instance, Yosys has been widely used for behavioral synthesis since 2012 and Project Icestorm, the first fully open-source FPGA design flow has been available since 2015; together they enabled Trenz Electronic’s icoBOARD, a Raspberry Pi accessory that could be programmed entirely using its ARM CPU, a platform not otherwise supported by the vendor. The availability of low-cost FPGA development boards such as the icoBOARD, TinyFPGA, IceZUM Alhambra, the iceBreaker board, amongst others have also played a part in fostering this “Open FPGA” movement. With OpenLANE and the Skywater process development kit, an open-source tool flow emerged that synthesizes RTL models to GDSII, gracefully enabling open-source ASIC design. The advantages of open design automation — as Linux has provided for operating systems — are many: unrestricted research and development, improved quality due to competition, teaching benefits, as well as lowering the barrier and risk to entry, and time to market, of start-ups for building novel applications, tools, and silicon. With such an open-source ecosystem in place, ASICs and reprogrammable logic could achieve the same success and inspire the next generation of hardware engineers as the Raspberry Pi has done for software engineers.

OSDA intends to provide an avenue for industry, academics, and hobbyists to collaborate, network, and share their latest visions and open-source contributions, with a view to promoting reproducibility and re-usability in the design automation space. DATE provides the ideal venue to reach this audience since it is the flagship European conference in this field — particularly poignant due to the recent efforts across the European Union (and beyond) that mandate “open access” for publicly funded research to both published manuscripts as well as software code necessary for reproducing its conclusions. A secondary objective of this workshop is to provide a peer-reviewed forum for researchers to publish “enabling” technology such as infrastructure or tooling as open-source contributions — standalone technology that would not normally be regarded as novel by traditional conferences — such that others inside and outside of academia may build upon it.


We request contributions of the following topics, including but not limited to:

  • Open-source EDA tools — the latest developments, breakthroughs, challenges and surveys on the toolflows required to target real silicon parts: synthesis, verification, place and route, etc.
  • Open-source IP — contributions that enrich the IP ecosystem and reduce the need to “re-invent the wheel”, e.g. PCIe and DDR controllers, debug infrastructure, etc.
  • Design methodologies provided as open-source — such as hardware description languages (e.g. MyHDL, Chisel), domain specific (DSL), high level synthesis (HLS), or asynchronous methods.
  • Directions on where the open-source EDA movement should go, current weaknesses in the toolchain, and/or perspectives from industry on how open-source can affect aspects of safety, security, verification, IP protection, time-to-market, datacenter/cloud infrastructure, etc.
  • Discussions and case studies on how to license, acquire funding, and commercialize technologies surrounding open-source hardware, which may be different to open software.



Larry Doolittle

Senior Scientist/Engineer at Lawrence Berkeley National Labs

vhd2vl is a simple and open-source stand-alone program that converts synthesizable VHDL to Verilog. While it has plenty of limitations, it has proved useful to many developers since its start in 2004. This talk will cover its strengths, weaknesses, and alternatives.


Antonino Tumeo

Chief Scientist at Pacific Northwest National Laboratory (PNNL)

This talk presents the SODA (Software Defined Accelerators) framework, an open-source modular, multi-level, no-human-in-the-loop, hardware compiler that enables end-to-end generation of specialized accelerators from high-level data science frameworks. SODA is composed of SODA-Opt, a high-level frontend developed in MLIR that interfaces with domain-specific programming environments and allows performing system level design, and Bambu, a state-of-the-art high-level synthesis (HLS) engine that can target different device technologies. The framework implements design space exploration as compiler optimization passes. We show how the modular, yet tight, integration of the high-level optimizer and lower-level HLS tools enables the generation of accelerators optimized for the computational patterns of novel “converged” applications. We then discuss some of the research opportunities that such an open-source framework allows.


Matthew Guthaus

Professor at University of California Santa Cruz

In this talk, Prof. Guthaus presents the current status of the OpenRAM project including Skywater 130 tape-out results. In addition, Prof. Guthaus will discuss the future roadmap of the OpenRAM project features and support for newer technologies.


Tsung-Wei Huang

Assistant Professor at University of Utah

Today’s EDA algorithms demand large parallel and heterogeneous computing resources for performance. However, writing parallel EDA algorithms is extremely challenging due to highly complex and irregular patterns. This talk will present a novel programming system to help tackle the parallelization challenges of building high-performance EDA algorithms.


Tim Edwards

VP Analog at Efabless, Inc.

This talk explores how hardware projects designed using an open source PDK rely too much on precise data which may not be available, and how problems can be avoided by certain design methodologies such as two-phase clocking, negative-edge clocking, margining, and monte carlo simulation. While open PDK data can be made more reliable by cross validation with multiple tools and, ultimately, measurement, good design practices can achieve working silicon without absolute certainty.


Rishiyur Nikhil

Co-founder and CTO at Bluespec Inc.

BSV and BH, the Bluespec HLHDLs (High-Level Languages for Hardware Design), emerged from ideas in formal specification (Term Rewriting Systems), functional programming (Haskell), and automatic synthesis of RTL from specifications. BSV has been used in some major commercial ASIC designs and is used widely in FPGA projects. The BSV/BH compiler (written in Haskell) was open-sourced in 2020 ( and today’s projects are centered around RISC-V design and verification, and on accelerators.


Frans Skarman

Spade is a new open source hardware description language (HDL) designed to increase developer productivity without sacrificing the low-level control offered by HDLs. It is a standalone language which takes inspiration from modern software languages, and adds useful abstractions for common hardware constructs. It also comes with a convenient set of tooling, such as a helpful compiler, a build system with dependency management, tools for debugging, and editor integration.


Poster Session (Coffee Break)

  • Davide Cieri, Nicolò Vladi Biesuz, Rimsky Alejandro Rojas Caballero, Francesco Gonnella, Nico Giangiacomi, Guillermo Loustau De Linares and Andrew Peck: Hog 2023.1: a collaborative management tool to handle Git-based HDL repository
  • Lucas Klemmer and Daniel Grosse: Programming Language Assisted Waveform Analysis: A Case Study on the Instruction Performance of SERV
  • Vamsi Vytla and Larry Doolittle: Newad: A register map automation tool for Verilog
  • Stefan Riesenberger and Christian Krieg: Towards Power Characterization of FPGA Architectures To Enable Open-Source Power Estimation Using Micro-Benchmarks


Andrew Kahng

Professor at University of California San Diego

OpenROAD ( is an open-source RTL-to-GDS tool that generates manufacturable layout from a given hardware description – in 24 hours, at advanced foundry nodes. OpenROAD lowers the cost, expertise and schedule barriers to hardware design, thus providing a platform for research, education and system innovation. This talk will present current status of the OpenROAD project and the roadmap for OpenROAD as it seeks to enable VLSI/EDA education, early design space exploration for system designers, research on machine learning in EDA, and more.


Jean-Paul Chaput

Engineer at Sorbonne Université

The talk will be focused on two majors points : why Open Hardware is as important as Open Source Software and the major challenges in building FOSS EDA tools.


Myrtle Shah

PhD student at Heidelberg University

Myrtle will introduce some of the recent developments in nextpnr; including easier ways of prototyping new architectures as well as some core algorithm improvements. They will also introduce FABulous, a highly flexible open source eFPGA fabric generator, and its close integration with nextpnr.


Tristan Gingold

HDL Developer at CERN

GHDL is an open-source VHDL simulator and synthesis tool. This talk will present the latest added features and some ideas for future development (in particular mixed simulation)


Jim Lewis

OSVVM Architect at SynthWorks

Open Source VHDL Verification Methodology (OSVVM) provides VHDL with buzz word verification capabilities including Transaction Level Modeling, Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, Error and Message handling, and Test Reporting that are simple to use and feel like built-in language features. OSVVM has grown rapidly during the COVID years, giving us better capability, better test reporting (HTML and Junit), and scripting that is simple to use (and works with most VHDL simulators). This presentation shows how these advances fit into the overall OSVVM Methodology.


Claire Xenia Wolf

CTO at YosysHQ

In her talk, Claire will discuss recent developments in open-source verification tools. Claire will briefly present equivalence checking with Yosys (EQY) and mutation cover with Yosys (MCY), and will highlight potential future directions.


Flanders Meeting & Convention Center Antwerp
Antwerp, Belgium + Google Map

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