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Improving Efficiency and Quality of Verification Environments with Automation

Bugs can be introduced at any stage in the hardware design development process and escape into tapeout if the verification environment is unqualified. Measuring and improving verification effectiveness to prevent bugs during functional verification is the key to taping out bug-free high-quality designs. Verification environments are often more complex than the designs they help verify.… Improving Efficiency and Quality of Verification Environments with Automation