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Improving Efficiency and Quality of Verification Environments with Automation
October 18 @ 10:00 am - 11:00 am PDT
Bugs can be introduced at any stage in the hardware design development process and escape into tapeout if the verification environment is unqualified. Measuring and improving verification effectiveness to prevent bugs during functional verification is the key to taping out bug-free high-quality designs. Verification environments are often more complex than the designs they help verify. Traditional methods are good indicators of verification effectiveness but provide a partial picture. For example, code coverage measures activation, but neither propagation nor detection. Verification effectiveness increases by leaps and bounds with automation.
In this Synopsys webinar, Samsung Israel Research Center (SIRC) will share its methodology utilizing Synopsys Certitude to run automatically when a block reaches a certain level of maturity. Samsung will demonstrate how Certitude’s flow enables automatic sanity checks and verification of blocks, followed by routine reporting to the relevant engineer and manager, without any explicit effort from the user. Samsung experts will also showcase the various bugs identified using Synopsys Certitude on real projects.
Attendees will leave with knowledge of effective verification automation concepts and how they can gain 100% confidence and enhance their existing verification environment with Synopsys Certitude.