RISC
ASIP Virtual Seminar 2022
Extending RISC Processors into Flexible Accelerators using ASIP Designer Case Studies in Artificial Intelligence and Image Signal Processing The slow-down of Moore’s law and Dennard scaling has triggered an increased awareness of application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain, often starting from a baseline such… Read More »ASIP Virtual Seminar 2022
Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator? • Do you need to size the AI accelerator for existing and future AI requirements? • Would it be beneficial if you knew the latency advantage between ARM, RISC, DSP and Accelerator in deploying AI tasks? This webinar… Read More »Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)