ASIP Virtual Seminar 2022

The slow-down of Moore’s law and Dennard scaling has triggered an increased awareness of application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the acceleration domain, and thus more flexibility and agility in both the design process and the eventual product.  Maintaining a RISC-V ISA baseline facilitates compatibility with and reuse of existing processor ecosystem elements.

Synopsys’ ASIP Designer is the industry-leading tool to design, implement, program and verify application-specific instruction-set processors. Starting from a single processor specification, designers immediately obtain an optimizing C/C++ compiler, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop and synthesis-in-the-loop methodology, the ISA and microarchitecture can be tuned quickly to the application domain.

This seminar introduces you to the ASIP Designer tool-suite.  It features two case studies from popular application domains.  The first case study, by the University of Virginia, shows the design exploration for a RISC-V based accelerator for edge AI applications compiled from graph formalisms, combining TVM and ASIP Designer.  Performance and design productivity gains are illustrated for example deep neural networks and for matrix-based math computations.  The second case study, by Synopsys, shows an accelerator for image signal processing.  A RISC-V baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for stereo image matching.