Riviera-PRO
Increase your productivity with Continuous Integration flows
Abstract: In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has the potential to introduce new bugs into the design. Accordingly, when many changes are being made, it is difficult to pinpoint which one introduced new bugs, and much time can… Read More »Increase your productivity with Continuous Integration flows
Automating UVM flow using Riviera-PRO’s UVM Generator
UVM is a versatile verification methodology that enables users to run advanced verification flows for large scale FPGAs and SoC FPGAs. However, because of its advanced nature, writing UVM from scratch can be a complex and tedious task. Riviera-PRO’s new UVM Generator feature alleviates some of the complexity by automatically creating the UVM testbench for… Read More »Automating UVM flow using Riviera-PRO’s UVM Generator
Introduction to OpenCPI (US)
The Open Component Portability Infrastructure (OpenCPI) is an open source software (OSS) framework for developing and executing component-based applications on heterogeneous systems. By targeting heterogeneous systems, the framework supports development and execution across diverse processing technologies including GPPs (general purpose processors), FPGA (field programmable gate arrays), and GPUs (graphics processing units) assembled into mixed systems.… Read More »Introduction to OpenCPI (US)
System Simulation of Versal ACAP Designs
AVersal ACAP, developed by Xilinx/AMD, is a groundbreaking adaptable platform composed of AI Engine (AIE), Processing System (PS), Programmable Logic (PL), Network on Chip (NoC) and a wide range of hardened domain-specific IPs. Versal ACAP enables the efficient execution of complex algorithms and accelerates workloads, including machine learning, embedded computing, and high-performance computing. In this… Read More »System Simulation of Versal ACAP Designs
Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO
AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract, review and statically verify AXI bus interfaces. In addition, ALINT-PRO can assist with automatic generation of test harnesses for dynamic verification. For dynamic verification of AXI interconnects, Aldec provides FPGA vendor-agnostic AXI Bus… Read More »Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO