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Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO
January 25, 2024 @ 11:00 am - 12:00 pm PST

AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract, review and statically verify AXI bus interfaces. In addition, ALINT-PRO can assist with automatic generation of test harnesses for dynamic verification. For dynamic verification of AXI interconnects, Aldec provides FPGA vendor-agnostic AXI Bus Functional Models (BFM) as well as Riviera-PRO functional verification platform.
In this webinar, we will present AXI bus interface extraction and static verification with ALINT-PRO. Then, we will show how ALINT-PRO assists in test harness wrapper generation for dynamic verification with Riviera-PRO. Finally, we will show the usage of Aldec AXI BFM solution for dynamic interconnect verification.
Agenda:
- Bus interfaces extraction
- Bus interfaces static verification
- Test harness development (script-based)
- Aldec AXI BFM overview
- Dynamic verification of AXI interconnect design using Aldec AXI BFM and Riviera-PRO
- Live demo
- Conclusion
- Q&A
Webinar Duration
- 45 min presentation/live demo
- 15 min Q&A
Presenter
Bio:
Alex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.