Stratus HLS
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Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers
Power Shutoff is a popular technique for saving power during functionally idle periods. Implementing Power Shutoff requires a detailed understanding of which resisters must be retained to enable bring-up from the power-off state. Identifying the minimal set of retention registers is challenging and grows more difficult with design complexity. This CadenceTECHTALK introduces a novel High-Level… Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers
From MATLAB to Optimized RTL in Minutes
As semiconductor process technology advances, predicting and achieving design power, performance, and area (PPA) goals become increasingly difficult. Developing high-performance algorithms for AI and signal processing is particularly challenging as algorithm development is abstracted from design implementation, often resulting in late discovery of performance issues. To mitigate this challenge, Cadence and MathWorks have collaborated to… From MATLAB to Optimized RTL in Minutes