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From MATLAB to Optimized RTL in Minutes

September 22 @ 12:00 pm - 1:00 pm PDT

Cadence, September 22, 2022

As semiconductor process technology advances, predicting and achieving design power, performance, and area (PPA) goals become increasingly difficult. Developing high-performance algorithms for AI and signal processing is particularly challenging as algorithm development is abstracted from design implementation, often resulting in late discovery of performance issues. To mitigate this challenge, Cadence and MathWorks have collaborated to deliver the industry’s first integration of Stratus High-Level Synthesis (HLS) and MATLAB. This integration provides early PPA measurement to enable data-driven algorithm development and automated production of optimized RTL.

Join us for a one-hour webinar to learn how this integration shortens design schedules and delivers designs with superior PPA. This technical webinar discusses the integration in detail and features a demonstration of the technology applied to a real-world design.

Speakers:

Jeff Roane

Director Product Management, Cadence Stratus HLS

Sarmad Dahir

Principal Application Engineer, Cadence DSG​

Eric Cigan

MathWorks HDL/SoC Product Marketing

Details

Date:
September 22
Time:
12:00 pm - 1:00 pm PDT
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Cadence
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