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IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis

Cadence Design Systems, Building 5 2655 Seely Avenue, San Jose, CA, United States

Power integrity (PI) is a major challenge for chip designers in the era of ubiquitous data, hyperconnectivity, and AI. Design size is exploding, and innovations in heterogenous integration are adding to PI complexity. These changes and challenges are ushering in the IR2.0 era ― a new paradigm for power integrity design and analysis. As a… Read More »IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis