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Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This Synopsys webinar demonstrates the verification of… Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
Verify Your SoC Design Efficiently from Planning to Coverage Closure using Synopsys Verification Family
Verifying an SoC is an extremely complex process that requires agile turnaround, constant control feedback, and flexibility to adapt to evolving project needs. Coverage is an efficient metric for the… Verify Your SoC Design Efficiently from Planning to Coverage Closure using Synopsys Verification Family
Everything You Need to Know about SystemVerilog Arrays
This webinar gives a comprehensive guide to all aspects of SystemVerilog arrays: ordinary static arrays, dynamic arrays, queues and associative arrays. It also includes array methods and practical examples. Topics:… Everything You Need to Know about SystemVerilog Arrays