VHDL
Latest Past Events
Using OSVVM’s AXI4 Verification Components
Abstract: This “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 2 of this presentation focuses on how to write tests and configure the AXI4 VCs. AXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity is due to the… Using OSVVM’s AXI4 Verification Components
Using OSVVM’s AXI4 Verification Components: Pt 1 Creating the AXI4 Testbench / Test Harness
European Session Abstract: This “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 1 of this presentation provides a detailed walkthrough of creating a testbench environment that uses AXI4 VCs. AXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity… Using OSVVM’s AXI4 Verification Components: Pt 1 Creating the AXI4 Testbench / Test Harness
Why Should Our Team be Using VHDL + OSVVM for Verification?
Abstract: This is a high-level presentation that identifies the key aspects of a modern verification methodology and shows how to achieve them with OSVVM. This is a great presentation to share with your management about why OSVVM (and OSVVM training) is important for your team. Description: Developing and deploying a verification methodology can be costly… Why Should Our Team be Using VHDL + OSVVM for Verification?