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Why Should Our Team be Using VHDL + OSVVM for Verification?

August 15, 2024 @ 11:00 am - 12:00 pm PDT

Aldec, August 15, 2024

Abstract:

This is a high-level presentation that identifies the key aspects of a modern verification methodology and shows how to achieve them with OSVVM. This is a great presentation to share with your management about why OSVVM (and OSVVM training) is important for your team.

Description:

Developing and deploying a verification methodology can be costly and time consuming. Going without one will be even more costly due to bugs escaping into production hardware systems.
Open Source VHDL Verification Methodology (OSVVM) provides the VHDL community with an already developed, open-source solution. OSVVM implements all of the capabilities of a modern verification methodology: transaction-based testing, a verification framework, verification components, self-checking tests, messaging handling, error tracking, requirements tracking, constrained random testing, scoreboards, functional coverage, co simulation with software, test automation, and a comprehensive set of test reports.
This presentation examines how these capabilities will benefit your projects.
SystemVerilog+UVM also provides a similar set of capabilities. Unfortunately, SV+UVM ended up absurdly complex to use – instead of using a module (entity/architecture in VHDL) with its built-in concurrency, SV+UVM uses OO, sequential code, and fork and join (to get concurrency). As a result, SV has failed to unify the design and verification communities.
VHDL+OSVVM on the other hand uses entity/architectures to create verification components and libraries of subprograms (procedures and functions) to extend VHDL into a complete verification language. In doing this, OSVVM creates verification capabilities that rival SystemVerilog+UVM while at the same time it uses VHDL language elements that are familiar to VHDL design engineers.
As a result, with VHDL+OSVVM and a good verification lead, any VHDL engineer can do verification as well as RTL design.

About OSVVM

OSVVM is a suite of libraries designed to streamline your VHDL entire verification process, boosting productivity and reducing development time. Each library provides independent capabilities, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing, OSVVM facilitates writing concise and readable test cases for both unit/RTL tests and complex FPGA and ASIC tests.

OSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling, verification components, co-simulation with software, randomized test generation, self-checking test support, verification data structures, comprehensive test reporting in HTML and text, and synchronization primitives.
With OSVVM and a good team lead, any VHDL engineer can do verification – and have fun doing it. As a result, having your entire team united in using OSVVM will simplify deploying VHDL engineers to projects.
SynthWorks has been using OSVVM for 25+ years in our training classes and consulting work. During that time, we have innovated new capabilities and evolved our existing ones to increase re-use and reduce effort and time spent.
Why VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study, in the FPGA market, 66% use VHDL for design, 58% use VHDL for verification, and 28% use OSVVM. Hence, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification.

 

Agenda
  • 50 min presentation/live demo
  • 10 min Q&A

 

Presenter Bio:

Jim Lewis, VHDL Design and Verification Expert, Trainer, OSVVM developer, and IEEE VHDL Chair

Jim Lewis, VHDL Design and Verification Expert, Trainer, OSVVM developer, and IEEE VHDL Chair

Jim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.
Whether teaching, developing OSVVM, consulting on VHDL design and verification projects, or working on the IEEE VHDL standard, Mr. Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.

Details

Date:
August 15, 2024
Time:
11:00 am - 12:00 pm PDT
Event Categories:
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Website:
Event Website

Organizer

Aldec
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