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Agnisys

Agnisys, December 7, 2023

Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques

Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints. Clock domain crossing… Read More »Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques

DVClub, November 28, 2023

Auto-generation of Verification Infrastructure for IP to SoC

Agenda (BST): Time Session Description Slides Videos 12.00 GMT Welcome and Introduction Mike Bartley,Tessolve 12.00 GMT Agnisys 12.30 GMT Imperas 12.45 GMT Breker 13.00 GMT… Read More »Auto-generation of Verification Infrastructure for IP to SoC

Agnisys, August 3, 2023

An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development

This webinar explores front-end automation advances that encompass an innovative register information management system to capture hardware functionality and addressable register map in a single… Read More »An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development

Agnisys, August 18, 2022

Centralized Register Design and Verification from a Golden Specification

Learn how to bring the ease of a document editor to your system architects and designers to create an executable specification using IDesignSpec™. This specification… Read More »Centralized Register Design and Verification from a Golden Specification