Skip to content
Agnisys, December 19, 2024

Advantages of using IP-XACT and TGI for SoC Development

Are you looking for ways to simplify your SoC development process, reduce rework, and accelerate time-to-market? Join us for an insightful webinar, “Advantages of using IP-XACT and TGI for SoC Development,” where we’ll explore how… Advantages of using IP-XACT and TGI for SoC Development

Agnisys, December 5, 2024

Optimizing Hardware Design with SystemRDL: Tools, Techniques, and Tips

Efficient management of registers and memory maps is critical for the success of modern System-on-Chip (SoC) designs. System Register Description Language (SystemRDL), combined with Agnisys’s IDesignSpec Suite, provides an advanced solution to automate and simplify… Optimizing Hardware Design with SystemRDL: Tools, Techniques, and Tips

DVClub Europe

DVClub Europe – AI/ML in Verification

This DVClub will consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to design verification. Agenda (GMT): Time Session Description Slides Videos 12.00 GMT Welcome and Introduction –… DVClub Europe – AI/ML in Verification

DVCon Europe, October 2024

Cocotb 2.0: Modernize your testbenches for even more productivity

Cocotb 2.0 is the latest major version of cocotb, ironing out many quirks that have accumulated over the years. With only small changes to your testbenches, you can benefit from improved typing and less surprising… Cocotb 2.0: Modernize your testbenches for even more productivity

DVClub Europe, 23 April 2024

DVClub Europe – Formal Verification

13 days to go the next DVClub Europe meeting takes place on Tuesday 23rd April with a theme of “Formal Verification“. Formal Verification can help you find bugs earlier in the design cycle and accelerate root cause analysis. But… DVClub Europe – Formal Verification

DVClub Europe, 19 March 2024

DVClub Europe: Latest VHDL Verification Techniques

This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM Agenda (GMT) 13:00   Welcome and Introduction – Mike Bartley, Tessolve 13:00   Epsen Tallaksen, EmLogic – Get the right FPGA quality through efficient… DVClub Europe: Latest VHDL Verification Techniques