TechNES FPGA Front Runner Event
The FPGA Front Runners event will be hosted by Renishaw at their venue in Wotton-under-Edge. The event will focus on “Using AI in development and… Read More »TechNES FPGA Front Runner Event
AI/ML
DVClub India – Using AI/ML in Design Verification
This DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification. Venue – Cadence Design System,… Read More »DVClub India – Using AI/ML in Design Verification
DVClub Europe – AI/ML in Verification
This is to inform you that the next DVClub Europe meeting takes place on Tuesday 17th October with a theme of “AI/ML in Verification”. This DVClub consider… Read More »DVClub Europe – AI/ML in Verification
ISQED Symposium 2024
A pioneer and leading interdisciplinary conference, the 25thInternational Symposium on Quality Electronic Design (ISQED’24) accepts and promotes original and unpublished papers related to the topics… Read More »ISQED Symposium 2024
CAD for Assurance: Panel 5: Hardware Assurance vs. AI: Friend or Foe?
Moderators: Ankur Srivastava (U. of Maryland) and Swarup Bhunia (U. of Florida) Panelists: – Mike Borza, Synopsys – Brian Night, Microsoft – Pompei Len Orlando,… Read More »CAD for Assurance: Panel 5: Hardware Assurance vs. AI: Friend or Foe?
Memory Bandwidth Races Higher with HBM3
With the formal release of the HBM3 specification, memory bandwidth for AI/ML and HPC shifts to a higher gear. Terabytes of bandwidth are possible using… Read More »Memory Bandwidth Races Higher with HBM3
59th DAC
The Design Automation Conference (DAC) is the premier event devoted to the design and design automation of electronic systems and circuits. DAC focuses on the… Read More »59th DAC
How to Overcome the Pain Points of AI/ML Hardware Design
Join Achronix for a live Webinar December 16th: 10-11 AM Pacific and Recorded On-Demand After the Event AI/ML hardware faces three common pain points: memory… Read More »How to Overcome the Pain Points of AI/ML Hardware Design