ALINT-PRO

Aldec, January 25,2024

Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO

January 22, 2024

AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract, review and statically… Read More »Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO

Aldec, December 2, 2021

LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)

November 29, 2021

Abstract: Today’s FPGAs and SoC FPGAs use various types of bus interconnect – such as AXI, APB, AHB, Avalon or Wishbone – for both internal… Read More »LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)