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Synopsys, September 21, 2023

Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study

The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This Synopsys webinar demonstrates the verification of standard RISC-V ISA extensions. A… Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study

OSDA 2023

3rd Workshop on Open-Source Design Automation

Call for papers There is no doubt that proprietary EDA tools are successful, mature, and fundamental for hardware development. However, the “walled garden” approach created by closed-source tool flows can hamper novel FPGA/ASIC-based applications and… 3rd Workshop on Open-Source Design Automation