Presenter: Espen Tallaksen, CEO of EmLogic Thursday, May 5, 2022 Abstract: For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification… FPGA Verification Architecture Optimization with UVVM
The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality and reliability. The difference between a good and a bad design architecture can be about 50% of the… Webinar: FPGA Design Architecture Optimization
Presenter: Espen Tallaksen, CEO of EmLogic Thursday, October 14, 2021 Abstract: Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way,… The most error prone FPGA corner cases