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FPGA Verification Architecture Optimization with UVVM

May 5, 2022 @ 11:00 am - 12:00 pm PDT

Aldec, May 5, 2022

Presenter: Espen Tallaksen, CEO of EmLogic
Thursday, May 5, 2022


For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and developed with a focus on reuse. In this webinar, we will show you how to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture. We will also discuss the importance of testbench sequencer simplicity and how it can be used to control multiple VHDL Verification Components simultaneously.


  • Testbenches with basic architecture and their limitations
  • Components of an efficient and advanced testbench architecture
  • VHDL Verification Components (VVC)
  • Controlling and checking many interfaces simultaneously
  • UVVM, VVC Framework Testbench Sequencer
  • Conclusion
  • Q&A

Webinar Duration:

45 min presentation/live demo
15 min Q&A


May 5, 2022
11:00 am - 12:00 pm PDT
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