Skip to content
Cadence, November 2 2023

IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis

Power integrity (PI) is a major challenge for chip designers in the era of ubiquitous data, hyperconnectivity, and AI. Design size is exploding, and innovations in heterogenous integration are adding to PI complexity. These changes… IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis

TSMC 2023

TSMC 2023 North America OIP Ecosystem Forum

Learn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N2, N3/N3E/N3P/N3AE, N4/N4P, N5/N5A, N6/N6e/N6RF/N7, N12e, and N22 Latest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes, InFO, CoWoS®,… TSMC 2023 North America OIP Ecosystem Forum

proteanTecs, March 7, 2023

THE DATA REVOLUTION OF SEMICONDUCTOR PRODUCTION

The demand for efficient and scalable chip production has never been greater. The need to scale at volume and adapt to shorter innovation cycles makes machine learning and advanced data analytics essential components of semiconductor… THE DATA REVOLUTION OF SEMICONDUCTOR PRODUCTION

IEEECEDA, Feb 24, 2023

Hardware Security 2.0: What Are The New Frontiers?

The CAD for Trust and Assurance website is an academic dissemination effort by researchers in the field of hardware security. The goal is to assemble information on all CAD for trust/assurance activities in academia and… Hardware Security 2.0: What Are The New Frontiers?

CHIPS Alliance, 2022

CHIPS Alliance, Fall Technology Update

Join us in-person for our second biannual technology update featuring informative, technical talks on open source hardware collaborative development, hosted by Google and including speakers from Microsoft, Google, Intel, Antmicro, Efabless and others. CHIPS’ Thursday… CHIPS Alliance, Fall Technology Update