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Synopsys, September 5, 2024

Synopsys Processor IP Summit 2024: RISC-V, DSP and NPU IP for Your Diverse SoC Processing Needs

As electronic systems continue to become more complex and integrate greater functionality, SoC developers are faced with the challenge of developing more powerful, yet more energy-efficient devices. The processors used in these applications must be… 

Mirabilis, April 18, 2024

Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP

Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent… 

Synopsys, December 20, 2022

Using Formal Datapath Validation to Verify AI Processor Computations

For over a decade, CPU and GPU design companies have been using Synopsys VC Formal Datapath Validation (DPV) app with its HECTOR™ technology to verify their data processing elements because traditional verification methods cannot exhaustively…