Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP

Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling and simulating a multi-die SoC in a matter of weeks. These models can be used for UCIe setup, task partitioning, distribution of compute resources across dies, sharing coherency between RISC-V clusters, GPU and AI Engines. We will show how workloads and application task graphs can be used to optimize the settings to meet the requirements, identify system bottlenecks and optimize for PPA. Results from actual hardware designs with different configurations and allocations will be discussed during the session.