Skip to content
Aldec. October 13, 2022

Assertions-Based Verification for VHDL Designs

Assertion-based verification (ABV) enables the use of assertions for the efficient verification of low-level design properties. These assertions could be verified by simulation and formal verification methods. The VHDL 2008 standard includes Property Specification language… Assertions-Based Verification for VHDL Designs

Aldec October 21

Using OVL for Assertion-based Verification of Verilog and VHDL Designs

Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation,… Using OVL for Assertion-based Verification of Verilog and VHDL Designs