Using OVL for Assertion-based Verification of Verilog and VHDL Designs

Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal verification and emulation. Also, the OVL-based verification technology provides the easiest way for designers to implement assertion-based verification of their design. Finally, OVL supports any HDL language (Verilog, SystemVerilog, VHDL), enabling assertion-based verification with any simulation tools.

Agenda:

• Assertion-Based Verification: An Overview
• Introduction to Assertion-Based Verification with OVL
• Applying OVL – based verification on HDL designs
• Using OVL checkers in emulation/prototyping
• Formal Model checking with OVL
• Live demo
• Conclusion
• Q&A

Presenter BIO

Alexander Gnusin, Design Verification Technologist. Alexander Gnusin accumulated 22 years of hands-on experience in various aspects of ASIC and FPGA design verification. His employees list includes IBM, Nortel and Synopsys Inc.