Missed milestones, lack of traceability, and costly respins. These are examples of what you risk if you do not take planning seriously during semiconductor design. A rock-solid planning process in the SOC Design process is…
Our customers are always coming to us with great questions, and in response discovering unique solutions, but we’ve never had a forum to share these learnings to our wider customer base. I’ve been considering a…
We’re already into the new year, so it was about time that I updated my list of Semi and EDA vendors that I’ve blogged or consulted for, here’s what changed: Mentor became Siemens EDA Moortec…