The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this… DVCON US 2025
Silicon photonics systems integrate photonic components such as optical waveguides, couplers, resonators, photodetectors, etc. along with electronic components on the same silicon chip to realize high-bandwidth, high-density, and low-power communication via wavelength-division multiplexing (WDM). This… Modeling and Simulation of Silicon Photonics Systems in SystemVerilog
The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this… DVCon USA 2024
ASP-DAC 2024 is the 29th annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most active regions of design, CAD and fabrication of silicon chips in the world.… ASP-DAC 2024
Chiplets are emerging as a new way of building IC systems via heterogeneous integration, and Universal Chip Interconnect Express (UCIe) is one of the standards defining the interconnects among chiplets. This webinar presents the SystemVerilog… UCIe PHY Modeling and Simulation with XMODEL
I found the first holiday video from Ansys posted on December 14th, so enjoy the photos and videos to bring you some cheer as 2022 winds down. Previous years: 2021 2020 2019 2018 2017 2016… Merry Christmas 2022
Learn how to write UVM testbenches for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes to build reusable and scalable testbenches for digital designs, and it can be extended to… Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification
It’s time for my annual Christmas and Holiday greetings from Semiconductor, #SemiEDA and #SemiIP companies. Send me your favorites. Past years: 2020 2019 2018 2017 2016 Happy holidays from all of us at Rambus! pic.twitter.com/ZfzZVgA3V9 — Rambus Inc.… Merry Christmas 2021
When verifying large SoC designs, one needs to write SystemVerilog models for analog/mixed-signal blocks to comply with the digital verification flow, such as UVM. This talk addresses ways to extract those models automatically from circuits.… Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example
