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Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example
September 15, 2021 @ 6:00 pm - 7:00 pm PDT
When verifying large SoC designs, one needs to write SystemVerilog models for analog/mixed-signal blocks to comply with the digital verification flow, such as UVM. This talk addresses ways to extract those models automatically from circuits.
The first approach is called structural modeling, mapping each device in the circuit to an equivalent model in SystemVerilog and connecting them up as they are in the original circuit. While this guarantees correct-by-construction models, the improvement in the simulation speed is limited due to the low abstraction level of the models.
The second approach is called functional modeling, aiming to raise the abstraction level of the models. One can select a part of the circuit and map it to one of the predefined model templates to generate its functional model. Although it requires some manual inputs, the resulting models can deliver significantly faster and even more accurate simulations than the structural models.
Question is, how many model templates would be necessary to model analog circuits? This talk shares my journey to answer this. I will use a pipelined analog-to-digital converter (ADC) example to demonstrate these different approaches.